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davicom semiconductor, inc. DM9006 10/100 mbps 2-port ethernet switch controller with general processor interface data sheet preliminary version: DM9006-ds-p01 september 1, 2009
DM9006 2-port switch with processor interface 2 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 content 1. general description............................................................................................. 10 2. block diagram......................................................................................................... 10 3. features .................................................................................................................... 11 4. pin configuration : 64 pin lqfp.......................................................................... 12 5. pin description ........................................................................................................ 13 5.1 processor bus interface .................................................................................................... ........................... 13 5.2 eeprom interfaces .......................................................................................................... ............................. 13 5.3 led pins ................................................................................................................... ...................................... 14 5.4 clock interface............................................................................................................ ................................... 14 5.5 network interface .......................................................................................................... ................................ 14 5.6 miscellaneous pins ......................................................................................................... .............................. 15 5.7 power pins ................................................................................................................. .................................... 15 5.8 strap pins table........................................................................................................... ................................... 15 6. control and status register set................................................................... 16 6.1 network control register (00h) ............................................................................................. ...................... 18 6.2 network status register (01h).............................................................................................. ....................... 18 6.3 tx control register (02h).................................................................................................. ........................... 18 6.4 rx control register (05h) .................................................................................................. .......................... 18
DM9006 2-port switch with processor interface preliminary datasheet 3 DM9006-13-ds-p01 september 1, 2009 6.5 rx status register (06h) ................................................................................................... ........................... 19 6.6 receive overflow counter register (07h) .................................................................................... .............. 19 6.7 flow control register (0ah)................................................................................................ ......................... 19 6.8 eeprom & phy control register (0bh) ........................................................................................ ............. 19 6.9 eeprom & phy address register (0ch) ........................................................................................ ........... 20 6.10 eeprom & phy data registers (0dh~0eh)..................................................................................... ........ 20 6.11 link change control register (0fh) ........................................................................................ ................. 20 6.12 processor port physical address registers (10h~15h) ....................................................................... .. 20 6.13 processor port multicast address registers (16h~1dh)...................................................................... .. 20 6.14 rx packet length low register ( 20h ) ..................................................................................... ............... 21 6.15 rx packet length high register ( 21h ) .................................................................................... ............... 21 6.16 rx additional status register ( 26h ) ..................................................................................... .................. 21 6.17 rx additional control register ( 27h ).................................................................................... .................. 21 6.18 vendor id registers (28h~29h) ............................................................................................. .................... 21 6.19 product id registers (2ah~2bh) ............................................................................................ ................... 21 6.20 chip revision register (2ch) .............................................................................................. ...................... 21 6.21 transmit check sum control register (31h) ................................................................................. .......... 21 6.22 receive check sum control status register (32h)........................................................................... ...... 22 6.23 up data bus driving capability register (38h) ............................................................................. ............ 22 6.24 irq pin control register (39h) ............................................................................................ ...................... 22
DM9006 2-port switch with processor interface 4 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 6.25 tx/rx memory size control register (3fh) .................................................................................. ........... 23 6.26 switch control register (52h)............................................................................................. ....................... 23 6.27 vlan control register (53h) ............................................................................................... ...................... 23 6.28 dsp phy control register (58h~59h)........................................................................................ ............... 24 6.29 per port control/status index register (60h).............................................................................. ............. 24 6.30 per port control data register (61h) ...................................................................................... .................. 24 6.31 per port status data register (62h) ....................................................................................... ................... 25 6.32 per port forward control register (65h) ................................................................................... ............... 25 6.33 per port ingress and egress control register (66h)........................................................................ ....... 26 6.34 per port bandwidth control setting register (67h) ......................................................................... ....... 27 6.35 per port block unicast ports control register (68h) . ...................................................................... ....... 28 6.36 per port block multicast ports control register (69h) ..................................................................... ...... 28 6.37 per port block broadcast ports control register (6ah)..................................................................... .... 28 6.38 per port block unknown ports control register (6bh) ....................................................................... ... 28 6.39 per port security & stp register (6ch).................................................................................... ................ 28 6.40 per port priority queue control register (6dh)............................................................................ ........... 29 6.41 per port vlan tag low byte register (6eh) ................................................................................. .......... 29 6.42 per port vlan tag high byte register (6fh)................................................................................ ........... 29 6.43 ethernet address control / status register 1 (70h) ........................................................................ ........ 30 6.44 ethernet address data register (71h~76h) .................................................................................. ........... 30 6.45 ethernet address control / status register 2 (77h) ........................................................................ ........ 30
DM9006 2-port switch with processor interface preliminary datasheet 5 DM9006-13-ds-p01 september 1, 2009 6.46 snooping control register 1 (78h)......................................................................................... ................... 31 6.47 snooping control register 2 (79h)......................................................................................... ................... 31 6.48 snooping control register 3 (7ah) ......................................................................................... .................. 32 6.49 snooping control register 4 (7bh) ......................................................................................... .................. 32 6.50 snooping control register 5 (7ch) ......................................................................................... .................. 32 6.51 mib counter port index register (80h) ..................................................................................... ................ 32 6.52 mib counter data registers (81h~84h) ...................................................................................... .............. 33 6.53 port-based vlan mapping table registers (b0h~bfh)......................................................................... 34 6.54 tos priority map registers (c0h~cfh)...................................................................................... .............. 34 6.55 vlan priority map registers (d0h~d1h) ..................................................................................... ............ 37 6.56 memory data pre-fetch read command without address increment register (f0h) ........................ 37 6.57 memory data read command with address increment re gister (f2h)................................................ 37 6.58 memory data read address register (f4h) ................................................................................... .......... 37 6.59 memory data read address register (f5h) ................................................................................... .......... 37 6.60 memory data write command without address increment register (f6h).......................................... 37 6.61 memory data write command with address increment register (f8h) ............................................... 38 6.62 memory data write address register (fah) .................................................................................. .......... 38 6.63 memory data write address register (fbh) .................................................................................. .......... 38 6.64 tx packet length registers (fch~fdh) ...................................................................................... ............ 38 6.65 interrupt status register (feh)........................................................................................... ....................... 38
DM9006 2-port switch with processor interface 6 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 6.66 interrupt mask register (ffh)............................................................................................. ....................... 38 7. eeprom format........... ............... ............... ............. ............. ............. ............. ........... 39 8. phy registers .......................................................................................................... 43 8.1 basic mode control register (bmcr) ? 00h ................................................................................... ........... 44 8.2 basic mode status register (bmsr) ? 01h .................................................................................... ............ 45 8.3 phy id identifier register #1 (phyid1) ? 02h............................................................................... .............. 46 8.4 phy id identifier register #2 (phyid2) ? 03h............................................................................... .............. 46 8.5 auto-negotiation advertisement register (anar) ? 04h....................................................................... ... 46 8.6 auto-negotiation link partner ability register (anlpar) ? 05h ............................................................. 4 7 8.7 auto-negotiation expansion register (aner) - 06h ........................................................................... ...... 48 8.8 davicom specified configuration register (dscr) ? 10h ...................................................................... 49 8.9 davicom specified configuration and status register (dscsr) ? 11h ................................................ 50 8.10 10base-t configuration/status (10btcsr) ? 12h............................................................................. ..... 51 8.11 power down control register (pwdor) ? 13h................................................................................. ....... 51 8.12 (specified config) register ? 14h ......................................................................................... ..................... 52 8.13 davicom specified receive error counter register (recr) ? 16h ..................................................... 53 8.14 davicom specified disconnect counter register (discr) ? 17h ........................................................ 53 8.15 power saving control register (pscr) ? 1dh ................................................................................ ......... 53 8.16 davicom indirect data register (data) ? 1eh ............................................................................... ..... 53 8.17 davicom indirect addr register (addr) ? 1fh............................................................................... ..... 53
DM9006 2-port switch with processor interface preliminary datasheet 7 DM9006-13-ds-p01 september 1, 2009 8.18 davicom indirect tx amplitude control register (tx_out_cntl) ? indirect-04h ........................... 54 9. functional description....................................................................................... 55 9.1 processor bus and memory management function: .............................................................................. ... 55 9.1.1 processor interface ...................................................................................................... ............................ 55 9.1.2 direct memory access control............................................................................................. .................... 55 9.1.3 packet transmission...................................................................................................... .......................... 55 9.1.4 packet reception ......................................................................................................... ............................ 55 9.2 switch function:........................................................................................................... .................................. 56 9.2.1 address learning ......................................................................................................... ............................ 56 9.2.2 address aging ............................................................................................................ .............................. 56 9.2.3 packet forwarding ........................................................................................................ ........................... 56 9.2.4 inter-packet gap (ipg) ................................................................................................... ......................... 56 9.2.5 back-off algorithm....................................................................................................... ............................. 56 9.2.6 late collision........................................................................................................... ................................. 56 9.2.7 half duplex flow control ................................................................................................. ........................ 56 9.2.8 full duplex flow control ................................................................................................. ......................... 57 9.2.9 partition mode ........................................................................................................... ............................... 57 9.2.10 broadcast storm filtering............................................................................................... ........................ 57 9.2.11 bandwidth control....................................................................................................... ........................... 57 9.2.12 port monitoring support ................................................................................................. ........................ 57 9.2.13 vlan support ............................................................................................................ ............................ 59 9.2.13.1 port-based vlan....................................................................................................... ......................... 59 9.2.13.2 802.1q-based vlan..................................................................................................... ...................... 59 9.2.13.3 tag/untag ............................................................................................................. .............................. 59 9.2.14 priority support ........................................................................................................ .............................. 59 9.2.14.1 port-based priority ................................................................................................... ........................... 60 9.2.14.2 802.1p-based priority................................................................................................. ......................... 60 9.2.14.3 diffserv-based priority............................................................................................... ......................... 60 9.2.15 address table accessing................................................................................................. ...................... 60 9.2.16 access rules of address table ........................................................................................... .................. 60 9.2.17 igmp snooping........................................................................................................... ........................... 63
DM9006 2-port switch with processor interface 8 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 9.2.18 port security........................................................................................................... ................................ 63 9.2.19 ipv6 mld snooping ....................................................................................................... ........................ 63 9.2.20 spanning tree protocol support.......................................................................................... .................. 64 9.3 internal phy functions ..................................................................................................... ............................. 65 9.3.1 100base-tx operation ..................................................................................................... ....................... 65 9.3.1.1 4b5b encoder ........................................................................................................... ............................ 65 9.3.1.2 scrambler .............................................................................................................. ................................ 65 9.3.1.3 parallel to serial converter ........................................................................................... ........................ 65 9.3.1.4 nrz to nrzi encoder .................................................................................................... ....................... 65 9.3.1.5 mlt-3 converter ........................................................................................................ ........................... 65 9.3.1.6 mlt-3 driver ........................................................................................................... .............................. 65 9.3.1.7 4b5b code group........................................................................................................ ......................... 66 9.3.2 100base-tx receiver ...................................................................................................... ........................ 67 9.3.2.1 signal detect .......................................................................................................... ............................... 67 9.3.2.2 adaptive equalization.................................................................................................. .......................... 67 9.3.2.3 mlt-3 to nrzi decoder.................................................................................................. ...................... 67 9.3.2.4 clock recovery module .................................................................................................. ...................... 67 9.3.2.5 nrzi to nrz ............................................................................................................ ............................. 67 9.3.2.6 serial to parallel ..................................................................................................... ............................... 67 9.3.2.7 descrambler ............................................................................................................ .............................. 67 9.3.2.8 code group alignment................................................................................................... ....................... 68 9.3.2.9 4b5b decoder........................................................................................................... ............................ 68 9.3.3 10base-t operation....................................................................................................... .......................... 68 9.3.4 collision detection ...................................................................................................... ............................. 68 9.3.5 carrier sense ............................................................................................................ ............................... 68 9.3.6 auto-negotiation ......................................................................................................... ............................. 68 10. dc and ac electrical characteristics ..................................................... 69 10.1 absolute maximum ratings .................................................................................................. ..................... 69 10.2 operating conditions...................................................................................................... ............................ 69 10.3 dc electrical characteristics ............................................................................................. ........................ 70
DM9006 2-port switch with processor interface preliminary datasheet 9 DM9006-13-ds-p01 september 1, 2009 10.4 ac characteristics ........................................................................................................ ............................... 71 10.4.1 power on reset timing ................................................................................................... ...................... 71 10.4.2 processor i/o read timing............................................................................................... ..................... 72 10.4.3 processor i/o write timing .............................................................................................. ...................... 73 10.4.4 eeprom timing ........................................................................................................... .......................... 74 11. package information........................................................................................ 75 12. ordering information ...................................................................................... 76
DM9006 2-port switch with processor interface 10 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 1. general description the DM9006 is a fully integrated and cost-effective fast ethernet switch controller with two ports 10m/100m phy, and general processor bus interface. the integrated two ports phy are compliant with ieee 802.3u standards and support hp auto-mdix capabilities for twisted-pair cable transmit/receive direction automatic switching. the general processor bus can be configured as 8-bit or 16-bit data width. the DM9006 is a managed switch, not only provides basic layer-2 switch functions but offers advanced features that include 802.1q vlan, priority queuing management, bandwidth rate control, monitoring port traffic, multicast packet filtering, port security and hardware-based igmp v1/v2 snooping, etc. the general processor bus can be configured as 8-, 16-, or 32-bit data width and interfaces to most embedded cpu. the DM9006 provides tcp/udp/ipv4 checksum offload function to alleviate host cpu load for improved system performance. the adjustable transmit/receive buffer of processor port can facilitate cpu in processing applications such as video and voice streaming. for power management feature, the DM9006 support wake on lan function via link status change or magic packet detection. additionally, the mib counters, loop-back capability and the memory build-in self test (bist) are useful for system and board level diagnostic. 2. block diagram 10 / 100 m phy 10/ 100 m mac 10/ 100 m phy 10/ 100 m mac port 0 mdi / mdix port 1 mdi / mdix switch controller control registers mib counters eeprom interface embedded memory memory bist memory management processor interface host mac switch engine 8 / 16 bit processor bus eeprom switch fabric
DM9006 2-port switch with processor interface preliminary datasheet 11 DM9006-13-ds-p01 september 1, 2009 3. features ? ethernet switch with two 10/100mb phy, and a flexible 8-bit or 16-bit general processor bus interface ? store and forward switching approach ? support hp auto-mdix ? support up-to 1k unicast mac addresses ? support ieee 802.3x flow control in full-duplex mode ? support back pressure flow control in half-duplex mode ? per port supports ingress or egress bandwidth rate control ? support broadcast/multicast storm suppression ? support maximum packet length up to 1536(default)/2032 bytes ? support head of line (hol) blocking prevention ? support mib counters for diagnostic ? general processor bus is slave architecture ? general processor bus driving capability is adjustable ? general processor bus supports tcp/udp/ipv4 checksum offload ? eeprom interface for power up configuration ? support eeprom 93c46/93c56 with auto-detecting ? driving capability of txd/txe of mii is adjustable ? per port supports 4 level priority queues by port-based, 802.1p vlan, and ip tos priority. the priority queue can be set at wrr(weight ed round robin) or strictly(high priority queue first) ? support 802.1q vlan up-to 16 vlan group. ? support vlan id tag/untag options ? mac address table is accessible ? support 256-entry multicast address table ? support port security function ? support 32 entry hardware-based igmp snooping v1, v2 ? up data driving capability adjustable ? 64-pin lqfp 1.8v internal core, 3.3v i/o with 5v tolerant ? support lead-free and halogen?free
DM9006 2-port switch with processor interface 12 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 4. pin configuration : 64 pin lqfp 11 32 31 30 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 29 28 27 26 25 vref gnd x2 gnd vcc3 lnk0_led spd0_led test2 cmd cs# iow# gnd vcc3 ior# sd7 irq sd1 sd4 vcci vcc3 sd6 gnd sd2 sd13 vcntl test1 gnd sd15 sd14 eedio pwrst# vcc3 sd12 sd9 sd8 eecs gnd sd0 eeck sd10 49 50 51 52 53 54 55 56 57 58 59 60 61 63 64 62 vcci spd1_led x1 lnk1_led sd11 sd3 sd5 gnd 36 37 38 39 40 41 42 43 44 45 46 33 34 35 48 47 avddi tx1+ tx1- agnd rx1+ rx1- avdd3 avddi tx0+ tx0- agnd rx0+ rx0- avdd3 bgres bgresg DM9006
DM9006 2-port switch with processor interface preliminary datasheet 13 DM9006-13-ds-p01 september 1, 2009 5. pin description i = input, o = output, i/o = input / output, o/d = open dr ain, p = power, pd=internal pull-low (approx. 50k ohm) # = asserted low 5.1 processor bus interface pin no. pin name i/o description 2 ior# i processor read command default is low active. the polarity can be changed by setting eeprom. 3 irq o interrupt request default is high active and non-open collector type. its polarity and output type can be changed by strap pins or eeprom setting. 5,6,7,9,10,12,14,15, 17,18,19,20,21,22,24,25 sd0~15 i/o processor data bus bit 0~15 60 cmd i command type upon the io transaction, when cmd is high, sd0~15 reflect the value of data port when cmd is low, sd0~15 reflect the value of index port 62 cs# i processor chip select command default is low active. its polarity can be changed by eeprom setting. 63 iow# i processor write command default is low active. its polarity can be changed by eeprom setting. 5.2 eeprom interfaces pin no. pin name i/o description 27 eedio i,/o eeprom data in/out 28 eeck o,pd eeprom serial clock this pin is used as the clock for the eeprom data transfer. 29 eecs o,pd eeprom chip selection.
DM9006 2-port switch with processor interface 14 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 5.3 led pins pin no. pin name i/o description 55 lnk1_led o/d port 1 link / active led it is the combined led of link and carrier sense signal of the port 1. 56 spd1_led o/d port 1 speed led it?s low to indicate that the port 1 operates in 100m mode. it?s floating to indicate that the port 1 operates in 10m mode. 57 lnk0_led o/d port 0 link / active led it is the combined led of link and carrier sense signal of the port 0. 58 spd0_led o/d port 0 speed led it?s low to indicate that the port 0 operates in 100m mode. it?s floating to indicate that the port 0 operates in 10m mode. 5.4 clock interface pin no. pin name i/o description 52 x1 i crystal 25mhz in 53 x2 o crystal 25mhz out 5.5 network interface pin no. pin name i/o description 34,35 tx1+/- i/o port 1 tp tx these two pins are the transmit output in mdi mode or the receive input in mdix mode. 37,38 rx1+/- i/o port 1 tp rx these two pins are the receive input in mdi mode or the transmit output in mdix mode. 41,42 tx0+/- i/o port 0 tp tx these two pins are the transmit output in mdi mode or the receive input in mdix mode. 44,45 rx0+/- i/o port 0 tp rx these two pins are the receive input in mdi mode or the transmit output in mdix mode. 47 bgres i/o band gap pin connect a 1.4kohm 1% resistor to bgresg in application. 48 bgresg p band gap ground 49 vcntl i/o 1.8v voltage control 50 vref o voltage reference connect a 0.1uf capacitor to ground in application.
DM9006 2-port switch with processor interface preliminary datasheet 15 DM9006-13-ds-p01 september 1, 2009 5.6 miscellaneous pins pin no. pin name i/o description 30 pwrst# i power-on reset low active with minimum 1ms 32 test1 i,pd tie to ground in application 59 test2 i,pd tie to ground in application 5.7 power pins pin no. pin name i/o description 1,13,26,51 vcc3 p digital 3.3v 11,61 vcci p internal 1.8v core power 4,8,16,23,31,54,64 gnd p digital gnd 39,46 avdd3 p analog 3.3v power 33,40 avddi p analog 1.8v power 36,43 agnd p analog gnd 5.8 strap pins table 1: pull-high 1k~10k, 0: floating (default). pin no. pin name description 28 eeck processor data bus width 0: 16-bit, sd 0-15 is used as processor data bus (default) 1: 8-bit, sd 0-7 is used as processor data bus; sd 8-15 is left floating. 29 eecs polarity of irq 0: irq pin high active (default) 1: irq pin low active
DM9006 2-port switch with processor interface 16 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 6. control and status register set the DM9006 implements several control and status registers (csr), which can be accessed by the host. all csr are set to their default values by power on or software reset unless specified. register description offset default value after reset ncr network control register 00h 00h nsr network status register 01h 00h tcr tx control register 02h 00h rcr rx control register 05h 00h rsr rx status register 06h 00h rocr receive overflow counter register 07h 00h fcr flow control register 0ah 00h epcr eeprom & phy control register 0bh 00h epar eeprom & phy address register 0ch 40h epdrl eeprom & phy low byte data register 0dh 00h epdrh eeprom & phy high byte data register 0eh 00h lccr link change control register (0fh) 0fh 00h par processor port physical address registers 10h-15h by eeprom mar processor port multicast address registers 16h-1dh xxh rxpllr rx packet length low register 20h 00h rxplhr rx packet length high register 21h 00h rasr rx additional status register 26h 00h racr rx additional control register 27h 00h vid vendor id registers 28h-29h 0a46h pid product id registers 2ah-2bh 9006h chipr chip revision registers 2ch 02h tcscr transmit check sum control register 31h 00h rcscsr receive check sum control status register 32h 00h driver up data bus driving capability register 38h 00h irqcr irq pin control register 39h 00h trmscr tx/rx memory size control register 3fh 00h switchcr switch control register 52h 00h vlancr vlan control register 53h 00h dsp1,2 dsp control register i,ii 58h~59h 0000h p_index per port control/status index register 60h 00h p_ctrl per port control data register 61h 00h p_stus per port status data register 62h 00h p_rate per port ingress and egress rate control register 66h 00h p_bw per port bandwidth control setting register 67h 00h p_unicast per port block unicast ports control register 68h 00h p_multi per port block multicast ports control register 69h 00h p_bcast per port block broadcast ports control register 6ah 00h p_unknwn per port block unknown ports control register 6bh 00h p_sstpr per port security & stp register 6ch 00h p_pri per port priority queue control register 6dh 00h
DM9006 2-port switch with processor interface preliminary datasheet 17 DM9006-13-ds-p01 september 1, 2009 vlan_tagl per port vlan tag low byte register 6eh 01h vlan_tagh per port vlan tag high byte register 6fh 00h p_mib_idx per port mib counter index register 80h 00h mib counter data register bit 0~7 81h 00h mib counter data register bit 8~15 82h 00h mib counter data register bit 16~23 83h 00h mib_dat mib counter data register bit 24~31 84h 00h pvlan port-based vlan mapping table registers b0-bfh 0fh tos_map tos priority map registers c0-cfh 00h~ffh vlan_map vlan priority map registers d0-d1h 50h,fah mrcmdx memory data pre-fetch read command without address increment register f0h xxh mrcmd memory data read command with address increment register f2h xxh mrrl memory data read_ address register low byte f4h 00h mrrh memory data read_ address register high byte f5h 00h mwcmdx memory data write command without address increment register f6h xxh mwcmd memory data write command with address increment register f8h xxh mwrl memory data write_ address register low byte fah 00h mwrh memory data write _ address register high byte fbh 00h txpll tx packet length low byte register fch xxh txplh tx packet length high byte register fdh xxh isr interrupt status register feh 00h imr interrupt mask register ffh 00h key to default in the register description that follows, the default column takes the form: , where: : 1 bit set to logic one 0 bit set to logic zero x no default value p = power on reset, by pwrst# pin, default value h = hardware reset, by reg. 52h bit 6, default value s = software reset, by reg. 00h bit 0, default value e = default value from eeprom setting t = default value from strap pin : ro = read only rw = read/write r/c = read and clear rw/c1=read/write and cleared by write 1 wo = write only reserved bits should be written with 0. reserved bits are undefined on read access.
DM9006 2-port switch with processor interface 18 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 6.1 network control register (00h) bit name default description 7 reserved 0,ro reserved 6 lnk_x_en p0,wo link change status enable when set, it enables to report port 0 or 1 link change status function. clearing this bit will also clear link change status this bit will not be affected after a software reset 5 clr1 ph0,rw 0: reg. 01h bit 2 and 3 can be auto-cleared after read 1: reg. 01h bit 2 and 3 can be cleared by writing 1 to respected bit. 4:2 reserved 0,ro reserved 1 lbk ph0, rw loopback test mode all transmit packets from processor port are forward to processor port itself. 0 rst ph0,rw software reset and auto clear after 10us 6.2 network status register (01h) bit name default description 7:6 reserved 0,ro reserved 5 link_x_st ph0, w/c1 link change status. this bit is set after port 0 or 1 link changed. this bit is cleared by write 1 4 reserved 0,ro reserved 3 tx2end phs0, rw/c1 tx packet 2 complete status. this bit is set after transmit completion of packet index 2 if bit 5 of ncr is set, this bit is cleared by write 1; otherwise it can be cleared by read or write 1. 2 tx1end phs0, rw/c1 tx packet 1 complete status. this bit is set after transmit completion of packet index 1 if bit 5 of ncr is set, this bit is cleared by write 1; otherwise it can be cleared by read or write 1. 1:0 reserved 0,ro reserved 6.3 tx control register (02h) bit name default description 7:4 reserved 0,ro reserved 3 crc_dis2 phs0,rw crc appends disable for packet index 2 2 reserved 0,ro reserved 1 crc_dis1 phs0,rw crc appends disable for packet index 1 0 txreq phs0,rw tx request. auto clears after transmit completely 6.4 rx control register (05h) bit name default description 7 hashall phs0,rw filter all address in hash table 6 reserved phs0,rw reserved 5 reserved phs0,rw reserved 4 dis_crc phs0,rw discard crc error packet 3 all phs0,rw pass all multicast packets all received packets with bit 0 is ?1? of destination address (da) field are accepted and save to receive memory. 2 reserved phs0,rw reserved
DM9006 2-port switch with processor interface preliminary datasheet 19 DM9006-13-ds-p01 september 1, 2009 1 prmsc phs0,rw promiscuous mode all received packets are accepted and save to receive memory without da field filter. 0 rxen phs0,rw rx enable 6.5 rx status register (06h) bit name default description 7 reserved 0,ro reserved 6 mf 0,ro multicast frame 5:4 pkt_type 0,ro received frame type 00: reserved 01: igmp packet 10: mld packet 11: bpdu packet 3:2 srcp 0,ro source port number 1 ce 0,ro crc error 0 foe 0,ro fifo overflow error 6.6 receive overflow counter register (07h) bit name default description 7 rxfu phs0,r/c receive overflow counter overflow this bit is set when the roc has an overflow condition 6:0 roc phs0,r/c receive overflow counter this is a statistic counter to indicate the received packet count upon fifo overflow 6.7 flow control register (0ah) bit name default description 7:6 reserved 0,ro reserved 5 flow_en phs0,rw rx flow control enable enables the pause packet for high/low water threshold control 4:0 reserved 0,ro reserved 6.8 eeprom & phy control register (0bh) bit name default description 7 reserved 0,ro reserved 6 eetype 0,ro eeprom type 0: 93c46 1: 93c56 5 reep ph0,rw reload eeprom. driver needs to clear it up after the operation completes 4 wep ph0,rw write eeprom enable 3 epos ph0,rw eeprom or phy operation select when reset, select eeprom; when set, select phy 2 erprr ph0,rw eeprom read or phy register read command. driver needs to clear it up after the operation completes. 1 erprw ph0,rw eeprom write or phy register write command. driver needs to clear it up after the operation completes.
DM9006 2-port switch with processor interface 20 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 0 erre ph0,ro eeprom access status or phy access status when set, it indicates that the eeprom or phy access is in progress 6.9 eeprom & phy address register (0ch) bit name default description 7:6 phy_adr ph01,rw phy address bit 1 and 0; the phy address bit [4:2] is force to 0. 5:0 eroa ph0,rw eeprom word address or phy register address 6.10 eeprom & phy data registers (0dh~0eh) bit name default description 7:0 epdrl ph0,rw eeprom or phy low byte data (0dh) this data is made to write/read low byte of word address defined in reg. 0ch to eeprom or phy 7:0 epdrh ph0,rw eeprom or phy high byte data (0eh) this data is made to write/read high byte of word address defined in reg. 0ch to eeprom or phy 6.11 link change control register (0fh) bit name type description 7:6 reserved 0,ro reserved 5 linken pe0,rw link change event enable when both set of this bit and bit 6 of ncr, it enables link change status event 4:3 reserved 0,ro reserved 2 linkst ph0,ro link change event status when set, it indicates that link status change event (link of port 0 or 1) occurred this bit can be cleared by write 1 to bit 5 of nsr or write 0 to bit 6 of ncr. 1:0 reserved 0,ro reserved 6.12 processor port physical address registers (10h~15h) bit name default description 7:0 pab5 e,rw physical address byte 5 (15h) 7:0 pab4 e,rw physical address byte 4 (14h) 7:0 pab3 e,rw physical address byte 3 (13h) 7:0 pab2 e,rw physical address byte 2 (12h) 7:0 pab1 e,rw physical address byte 1 (11h) 7:0 pab0 e,rw physical address byte 0 (10h) 6.13 processor port multicast address registers (16h~1dh) bit name default description 7:0 mab7 x,rw multicast address byte 7 (1dh) 7:0 mab6 x,rw multicast address byte 6 (1ch) 7:0 mab5 x,rw multicast address byte 5 (1bh) 7:0 mab4 x,rw multicast address byte 4 (1ah) 7:0 mab3 x,rw multicast address byte 3 (19h)
DM9006 2-port switch with processor interface preliminary datasheet 21 DM9006-13-ds-p01 september 1, 2009 7:0 mab2 x,rw multicast address byte 2 (18h) 7:0 mab1 x,rw multicast address byte 1 (17h) 7:0 mab0 x,rw multicast address byte 0 (16h) 6.14 rx packet length low register ( 20h ) bit name default description 7:0 rxpll ph,ro rx packet length low byte 6.15 rx packet length high register ( 21h ) bit name default description 7:0 rxplh ph,ro rx packet length high byte 6.16 rx additional status register ( 26h ) bit name default description 7:4 reserved 0,ro reserved 1:0 rptrs ph,ro up received pointer status, only available when rx pointer restriction is enabled (reg27h.7=0). 00: within buffer 01: end of buffer 1x: exceed buffer 6.17 rx additional control register ( 27h ) bit name default description 7 rprd phs0,rw rx pointer restriction disable 6:0 reserved 0,ro reserved 6.18 vendor id registers (28h~29h) bit name default description 7:0 vidh pe,0ah,ro vendor id high byte (29h) 7:0 vidl pe,46h.ro vendor id low byte (28h) 6.19 product id registers (2ah~2bh) bit name default description 7:0 pidh pe,90h,ro product id high byte (2bh) 7:0 pidl pe,06h.ro product id low byte (2ah) 6.20 chip revision register (2ch) bit name default description 7:0 chipr 02h,ro chip revision 6.21 transmit check sum control register (31h) bit name default description 7~3 reserved 0,ro reserved 2 udpcse hp0,rw udp checksum generation enable 1 tcpcse hp0,rw tcp checksum generation enable 0 ipcse hp0,rw ip checksum generation enable
DM9006 2-port switch with processor interface 22 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 6.22 receive check sum control status register (32h) bit name default description 7 udps hp0,ro udp checksum status 1: udp packet checksum is fail. 0: udp packet checksum is ok or it is not a udp packet. 6 tcps hp0,ro tcp checksum status 1: tcp packet checksum is fail. 0: tcp packet checksum is ok or it is not a tcp packet. 5 ips hp0,ro ip checksum status 1: ip packet checksum is ail 0: ip packet checksum is ok or it is not an ip packet. 4 udpp hp0,ro this is an udp packet 3 tcpp hp0,ro this is a tcp packet 2 ipp hp0,ro this is an ip packet 1 rcsen hps0,rw receive checksum checking enable when set, the checksum status will store in packet first byte of status header. 0 dcse hps0,rw discard checksum error packet when set, ip/tcp/udp checksum field is error, this packet will be discarded. 6.23 up data bus driving capability register (38h) bit name default description 7 reserved 0,rw reserved 6:5 isa_curr p01,rw sd bus current driving/sinking capability 00: 2ma 01: 4ma (default) 10: 6ma 11: 8ma 4:3 reserved p0,rw reserved 2 step p0,rw data bus output stepping 1: disabled 0: enabled 1 iow_spike p0,rw eliminate iow spike 1: eliminate about 2ns iow spike 0 ior_spike p1,rw eliminate ior spike 1: eliminate about 2ns ior spike 6.24 irq pin control register (39h) bit name default description 7:5 irq_delay ps0,rw irq delayed output interval this field determines the irq delayed output interval in multiples of 40 milliseconds(ms) 1 irq_type pet0,rw irq pin output type control 1: irq open-collector output 0: irq direct output
DM9006 2-port switch with processor interface preliminary datasheet 23 DM9006-13-ds-p01 september 1, 2009 0 irq_pol pet0,rw irq pin polarity control 1: irq active low 0: irq active high 6.25 tx/rx memory size control register (3fh) bit name default description 7:6 reserved ps0,ro reserved 5:0 tx_size p20h,rw tx block size this value defines the transmit block size in 256-byte unit. tx memory size = tx_size * 256 bytes and then rx memory size = 16kb ? (tx_size + 1)*256-byte note: the value of tx_size should be between 14h and 30h note 2: if the default value is chang ed, the reset switch command (reg52h bit 6) should be set to initialize DM9006 memory allocation. 6.26 switch control register (52h) bit name default description 7 mem_bist ph0,ro address memory test bist status 0: ok 1: fail 6 rst_sw p0,rw reset switch core and auto clear after 10us 5 rst_anlg p0,rw reset analog phy core and auto clear after 10us 4:3 snf_port phe00,rw sniffer port number define the port number to act as the sniffer port 2 crc_dis phe0,rw crc checking disable when set, the received crc error packet also accepts to receive memory. 1:0 reserved 0,ro reserved 6.27 vlan control register (53h) bit name default description 7 tos6 phe0,rw full tos using enable 1: check most significant 6-bit of tos 0: check most significant 3-bit only of tos 6 reserved 0,ro reserved 5 unicast phe0,rw unicast packet can across vlan boundary 4 vidfff phe0,rw replace vid fff if the received packet is a tagged vlan with vid equal to ?fff?, its vlan field is replaced with vlan tag defined in reg. 6eh and 6fh. 3 vid1 phe0,rw replace vid 001 if the received packet is a tagged vlan with vid equal to ?001?, its vlan field is replaced with vlan tag defined in reg. 6eh and 6fh. 2 vid0 phe0,rw replace vid 000 if the received packet is a tagged vlan with vid equal to ?000?, its vlan field is replaced with vlan tag defined in reg. 6eh and 6fh. 1 pri phe0,rw replace priority field in the tag with value define in reg 6fh bit 7~5.
DM9006 2-port switch with processor interface 24 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 0 vlan phe0,rw vlan mode enable 1: 802.1q base vlan mode enable 0: port-base vlan only 6.28 dsp phy control register (58h~59h) 58h: bit name default description 7:0 dsp_ctl1 ph0,rw dsp control register 1 for testing only (register 58h) 59h: bit name default description 7:0 dsp_ctl2 ph0,rw dsp control register 2 for testing only (register 59h) 6.29 per port control/status index register (60h) bit name default description 7:5 reserved phs0,rw reserved 4:2 reserved 0,ro reserved 1:0 index phs0,rw port index for register 61h~84h write the port number to this register before write/read register 61h~84h. note: the processor port index number is 3 6.30 per port control data register (61h) bit name default description 7 fast_lev phe0,rw igmp snooping fast leave enable 6 parti_en phe0,rw enable partition detection 5 no_dis_rx phe0,rw don?t discard rx packets when ingress bandwidth control when received packets bandwidth reach ingress bandwidth threshold, the packets over the threshold are not discarded but with flow control. 4 flow_dis phe0,rw flow control in full duplex mode, or back pressure in half duplex mode enable 0: enable 1: disable 3 bandwidth phe0,rw bandwidth control 0: control with ingress and egress separately, ref to register 66h. 1: control with ingress or egress, ref to register 67h 2 bp_dis phe0,rw broadcast packet filter 0: accept broadcast packets 1: reject broadcast packets 1 mp_dis phe0,rw multicast packet filter 0: accept multicast packets 1: reject multicast packets 0 mp_storm phe0,rw broadcast storm control 0: only broadcast packets storm are controlled 1: multicast packets also same as broadcast storm control.
DM9006 2-port switch with processor interface preliminary datasheet 25 DM9006-13-ds-p01 september 1, 2009 6.31 per port status data register (62h) bit name default description 7:6 reserved p0,ro reserved 5 lp_fcs p0,ro link partner flow control enable status 4 bist p0,ro bist status 1: sram bist fail 0: sram bist pass 3 reserved 0,ro reserved 2 speed2 p0,ro phy speed status 0: 10mbps, 1: 100mbps 1 fdx2 p0,ro phy duplex status 0: half-duplex, 1: full-duplex 0 link2 p0,ro phy link status 0: link fail, 1: link ok 6.32 per port forward control register (65h) bit name default description 7 loopback ph0,rw loop-back mode the received packet will be forward to this port itself. 6 moni_tx ph0,rw tx packet monitored the transmitted packets are also forward to sniffer port. 5 moni_rx ph0,rw rx packet monitored the received packets are also forward to sniffer port. 4 dis_bmp ph0,rw broad/multicast not monitored the received broadcast or multicast packets are not forward to sniffer port. 3 reserved ph0,rw reserved 2 tx_dis ph0,rw packet transmit disabled all packets can not be forward to this port. 1 rx_dis ph0,rw packet receive disabled all received packets are discarded. 0 adr_dis ph0,rw address learning disabled the source address (sa) field of packet is not learned to address table.
DM9006 2-port switch with processor interface 26 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 6.33 per port ingress and egress control register (66h) bit name default description 7:4 ingress phe0,rw ingress rate control these bits define the bandwidth threshold that received packets over the threshold are discarded. ingress rate table below 0000: none 0001: 64kbps 0010: 128kbps 0011: 256kbps 0100: 512kbps 0101: 1mbps 0110: 2mbps 0111: 4mbps 1000: 8mbps 1001: 16mbps 1010: 32mbps 1011: 48mbps 1100: 64mbps 1101: 72mbps 1110: 80mbps 1111: 88mbps 3:0 egress phe0,rw egress rate control these bits define the bandwidth threshold that transmitted packets over the threshold are discarded. egress rate table below 0000: none 0001: 64kbps 0010: 128kbps 0011: 256kbps 0100: 512kbps 0101: 1mbps 0110: 2mbps 0111: 4mbps 1000: 8mbps 1001: 16mbps 1010: 32mbps 1011: 48mbps 1100: 64mbps 1101: 72mbps 1110: 80mbps 1111: 88mbps
DM9006 2-port switch with processor interface preliminary datasheet 27 DM9006-13-ds-p01 september 1, 2009 6.34 per port bandwidth control setting register (67h) bit name default description 7:4 bsth phe0,rw broadcast storm threshold these bits define the bandwidth threshold that received broadcast packets over the threshold are discarded. threshold table below 0000: no broadcast storm control 0001: 8k packets/sec 0010: 16k packets/sec 0011: 64k packets/sec 0100: 5% 0101: 10% 0110: 20% 0111: 30% 1000: 40% 1001: 50% 1010: 60% 1011: 70% 1100: 80% 1101: 90% 111x: no broadcast storm control 3:0 bw ctrl phe0,rw received packet length counted. bandwidth table below these bits define the bandwidth threshold that transmitted or received packets over the threshold are discarded. bandwidth table below 0000: none 0001: 64kbps 0010: 128kbps 0011: 256kbps 0100: 512kbps 0101: 1mbps 0110: 2mbps 0111: 4mbps 1000: 8mbps 1001: 16mbps 1010: 32mbps 1011: 48mbps 1100: 64mbps 1101: 72mbps 1110: 80mbps 1111: 88mbps
DM9006 2-port switch with processor interface 28 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 6.35 per port block unicast ports control register (68h) bit name default description 7:4 reserved ph0,rw reserved 3:0 blk_up ph0,rw ports of unicast packet be blocked the received unicast packets are not forward to the assigned ports. note: that the assigned port definition: bit 0 for port 0, bit 1 for port 1, bit 2 reserved, and bit 3 for processor port. 6.36 per port block multicast ports control register (69h) bit name default description 7:4 reserved ph0,rw reserved 3:0 blk_mp ph0,rw ports of multicast packet be blocked the received multicast packets are not forward to the assigned ports. 6.37 per port block broadcast ports control register (6ah) bit name default description 7:4 reserved ph0,rw reserved 3:0 blk_bp ph0,rw ports of broadcast packet be blocked the received broadcast packets are not forward to the assigned ports. 6.38 per port block unknown ports control register (6bh) bit name default description 7:4 reserved ph0,rw reserved 3:0 blk_ukp ph0,rw ports of unknown packet be blocked the packets with da field not found in address table are not forward to the assigned ports. 6.39 per port security & stp register (6ch) bit name default description 7:6 reserved 0,ro reserved 5:4 stps ph0,rw spanning tree port state there are 4 port state for supporting spanning tree protocol 00: forwarding state, the port transmits and receives packets normally & learning is enabled. 01: disabled state, the port will not transmit and receive any packets & learning is disabled. 10: learning state, the port will only fo rward the packets that are to and from up port (span packets) & leaning is enabled. 11: blocking/listening state, the port will only forward the packets that are to and from up port (span packets) & leaning is disabled. 3 reserved 0,ro reserved 2 ps_unk phe0,rw unknown source address handling when port security is enabled 0: discard unknown (default) 1: unknown to up port
DM9006 2-port switch with processor interface preliminary datasheet 29 DM9006-13-ds-p01 september 1, 2009 1:0 ps_en phe0,rw port security enable 00: port security disable (default) 01: first lock 10: first link lock 11: assign lock 6.40 per port priority queue control register (6dh) bit name default description 7 tag_out phe0,rw output packet tagging enable the transmitted packets are containing vlan tagged field. 6 pri_dis phe0,rw priority queue disable only one transmit queue is supported in this port. 5 wfque phe0,rw weighted round-robin queuing 1: the priority weight for queue 3, 2, 1, and 0 is 8, 4, 2, and 1 respectively. 0: the queue 3 has the highest priority, and the next priorities are queue 2, 1, and 0 respectively. 4 tos_pri phe0,rw priority tos over vlan if an ip packet with vlan tag, the priority of this packet is decode from tos field. 3 tos_off phe0,rw tos priority classification disable the priority information from tos field of ip packet is ignored. 2 pri_off phe0,rw 802.1 p priority classification disable the priority information from vlan tag field is ignored. 1:0 p_pri phe0,rw port base priority the priority queue number in port base. 00 : queue 0, 01 : queue 1, 10 : queue 2, 11 : queue 3 6.41 per port vlan tag low byte register (6eh) bit name default description 7:0 vid70 phe01,rw vid[7:0] 6.42 per port vlan tag high byte register (6fh) bit name default description 7:5 pri phe0,rw tag [15:13] 4 cfi phe0,rw tag[12] 3:0 vid118 phe0,rw vid[11:8]
DM9006 2-port switch with processor interface 30 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 6.43 ethernet address control / status register 1 (70h) bit name default description 7 reserved 0,ro reserved 6:5 eacs p0,ro status of ethernet address command 00: command ok, entry non-exist a. create an new entry when command is write b. do nothing when command is delete c. entry not found when command is search d. entry is invalid when command is read 01: command ok, entry exist a. overwrite the entry when command is write b. delete entry when command is delete c. entry found when command is search d. entry is valid when command is read 1x: command error 4:3 eai phy,rw ethernet address table index 00: unicast address table 01: multicast address table 10: igmp table (read only) 11: reserved 2:1 eac ph0,rw ethernet address command 00: read 01: write 10: delete 11: search 0 eas p0,ro ethernet address table status 0: available 1: busy 6.44 ethernet address data register (71h~76h) bit name default description 71h ead0 ph0,rw mac address bit 07~00 72h ead1 ph0,rw mac address bit 15~08 73h ead2 ph0,rw mac address bit 23~16 74h ead3 ph0,rw mac address bit 31~24 75h ead4 ph0,rw mac address bit 39~32 76h ead5 ph0,rw mac address bit 47~40 6.45 ethernet address control / status register 2 (77h) bit name default description 7 reserved 0,ro reserved 6 override ph0,rw when writing table, this bit can set the entry to override the port?s setting in the receiving disable state of stp. when reading table, it indicates the entry is override one or not. this bit supports unicast and multicast address table both. 0: entry is normal one. 1: entry is override one.
DM9006 2-port switch with processor interface preliminary datasheet 31 DM9006-13-ds-p01 september 1, 2009 5 igmpe ph0,ro when reading multicast address table, this bit indicated the entry is igmp entry or not. 0: non-igmp entry 1: igmp entry 4 ea_static ph0,rw when writing unicast address table, this bit can be used to set the entry as static or dynamic. when reading unicast address tabl e, it indicates the entry is static or dynamic. 0: entry is dynamic. 1: entry is static, never be age-out 3:0 port ph0,rw forwarding port number (0~3), when access unicast address table. forwarding port mapping {up, p2, p1, p0}, when access multicast address table. 6.46 snooping control register 1 (78h) bit name default description 7 reserved 0,ro reserved 6:5 uipmpc phe0,rw unregistered ip multicast packet control the ip multicast packet with a destination address which does not match any of groups announced in earlier igmp membership reports, i.e. not found in the igmp membership table. 00: as normal multicast packets 01: dropped. 10: force forward to processor port. 11: forward to all ports except incoming & up port. 4 ud_igr phe0,rw user-defined igmp router port configuration enable 0: disable, the router portmap is automatic manipulation via igmp snooping. 1: enable, the router portmap is static defined by user. 3 sigs2up phe0,rw igmp packet forward to up port only when software-igs 2 higs2up phe0,rw igmp packet forward to up port also when hardware-igs 0: igmp packet doesn?t forwards to processor port when hardware based igmp snooping is enabled. 1: igmp packet also forwards to processor port when hardware based igmp snooping is enabled. 1 sigs_en phe0,rw software-based igmp snooping enable 0: hardware based igmp snooping, without software intervention. (default) 1: software based igmp snooping 0 igs_en phe0,rw igmp snooping enable 0: disable 1: enable 6.47 snooping control register 2 (79h) bit name default description 7 scp_pe phe0,rw snooping control packet priority enable 0: disable 1: enable 6:5 scp_pri phe0,rw snooping control packet priority 00: queue 0 01: queue 1 10: queue 2 11: queue 3
DM9006 2-port switch with processor interface 32 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 4:3 scp_otc phe0,rw snooping control packet output tag control 00: unmodified 01: always tagged 10: always untagged 11: reserved 2:0 rpp phe0,rw router port portmap if user-defined igmp router port configuration is enabled, this 3-bit register is used to define static router portmap, otherwise, this register is automatic manipulation by igmp snooping and read only. 6.48 snooping control register 3 (7ah) bit name default description 7:0 qi phe0,rw query interval define query interval when hardware-igs is enabled 6.49 snooping control register 4 (7bh) bit name default description 7:2 reserved 0,ro reserved 1:0 rv phe10,rw robustness variable define robustness variable when hardware-igs is enabled. 00 = reserved 01 = 1 times 10 = 2 times (default) 11 = 3 times 6.50 snooping control register 5 (7ch) bit name default description 7:2 reserved 0,ro reserved 1 mld2up phe0,rw mld packet forward to up port only. 0 mlds_en phe0,rw mld snooping enable 0: disable 1: enable 6.51 mib counter port index register (80h) bit name default description 7 ready p0,ro mib counter data is ready 6 mib_dis phs0,rw when write: 0: mib counter is enabled 1: mib counter is disabled when read: 0: mib counter is disabled 1: mib counter is enabled 5 reserved 0,ro reserved 4:0 index phs0,rw mib counter index 0~9, each counter is 32-bit in register 81h~84h. write the mib counter index to this register before read them.
DM9006 2-port switch with processor interface preliminary datasheet 33 DM9006-13-ds-p01 september 1, 2009 6.52 mib counter data registers (81h~84h) register name default description 81h mib_dat x,ro mib counter data register bit 0~7 82h mib_dat x,ro mib counter data register bit 8~15 83h mib_dat x,ro mib counter data register bit 16~23 84h mib_dat x,ro mib counter data register bit 24~31 mib counter: rx byte counter registers (index 00h) mib counter: rx uni-cast packet counter registers (index 01h) mib counter: rx multi-cast packet counter registers (index 02h) mib counter: rx discard packet counter registers (index 03h) mib counter: rx error packet counter registers (index 04h) mib counter: tx byte counter registers (index 05h) mib counter: tx uni-cast packet counter registers (index 06h) mib counter: tx multi-cast packet counter registers (index 07h) mib counter: tx discard packet counter registers (index 08h) mib counter: tx error packet counter registers (index 09h)
DM9006 2-port switch with processor interface 34 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 6.53 port-based vlan mapping table registers (b0h~bfh) define the port member in vlan group there are 16 vlan group that defined in reg. b0h~bfh. group 0 defined in reg. b0h, and group 1 defined in reg. b1h, and so on. bit name default description 7:4 reserved phe0,ro reserved 3 port_up phe1,rw mapping to processor 2 reserved phe1,rw reserved 1 port_p1 phe1,rw mapping to port 1 0 port_p0 phe1,rw mapping to port 0 6.54 tos priority map registers (c0h~cfh) define the 6-bit or 3-bit of tos field mapping to 2-bit priority queue number. in 6-bit type, the reg. 53h bit 7 is ?1?, reg. c0h bit [1:0] de fine the mapping for tos value 0, reg. 60h bit [3:2] define the mapping for tos value 1, and so on, till reg. cfh bit [7:6] define tos value 63. in 3-bit type, reg. 53h bit 7 is ?0? define the mapping for tos value 0, reg. 60h bit [3:2] define the mapping for tos value 1, and so on, till reg. c1h bit [7:6] define tos value 7. reg. c0h: bit name default description 7:6 tos3 phe0/1,rw if reg. 53h. bit 7 =1 :tos[7:2]=03h, otherwise tos]7:5]=03h 5:4 tos2 phe0,/1rw if reg. 53h. bit 7 =1 :tos[7:2]=02h, otherwise tos]7:5]=02h 3:2 tos1 phe0,rw if reg.53h. bit 7 =1 :tos[7:2]=01h, otherwise tos]7:5]=01h 1:0 tos0 phe0,rw if reg.53h. bit 7 =1 :tos[7:2]=00h, otherwise tos]7:5]=00h reg. c1h: bit name default description 7:6 tos7 phe0/3,rw if reg.53h. bit 7=1 :tos[7:2]=07h, otherwise tos]7:5]=07h 5:4 tos6 phe0/3,rw if reg.53h. bit 7=1 :tos[7:2]=06h, otherwise tos]7:5]=06h 3:2 tos5 phe0/2,rw if reg.53h. bit 7=1 :tos[7:2]=05h, otherwise tos]7:5]=05h 1:0 tos4 phe0/2,rw if reg.53h. bit 7=1 :tos[7:2]=04h, otherwise tos]7:5]=04h reg. c2h: bit name default description 7:6 tosb phe0,rw if reg.53h. bit 7=1 :tos[7:2]=0bh 5:4 tosa phe0,rw if reg.53h. bit 7=1 :tos[7:2]=0ah 3:2 tos9 phe0,rw if reg.53h. bit 7=1 :tos[7:2]=09h 1:0 tos8 phe0,rw if reg.53h. bit 7=1 :tos[7:2]=08h reg. c3h: bit name default description 7:6 tosf phe0,rw if reg.53h. bit 7=1 :tos[7:2]=0fh 5:4 tose phe0,rw if reg.53h. bit 7=1 :tos[7:2]=0eh 3:2 tosd phe0,rw if reg.53h. bit 7=1 :tos[7:2]=0dh 1:0 tosc phe0,rw if reg.53h. bit 7=1 :tos[7:2]=0ch
DM9006 2-port switch with processor interface preliminary datasheet 35 DM9006-13-ds-p01 september 1, 2009 reg. c4h: bit name default description 7:6 tos13 phe1,rw if reg.53h. bit 7=1 :tos[7:2]=13h 5:4 tos12 phe1,rw if reg.53h. bit 7=1 :tos[7:2]=12h 3:2 tos11 phe1,rw if reg.53h. bit 7=1 :tos[7:2]=11h 1:0 tos10 phe1,rw if reg.53h. bit 7=1 :tos[7:2]=10h reg. c5h: bit name default description 7:6 tos17 phe1,rw if reg.53h. bit 7=1 :tos[7:2]=17h 5:4 tos16 phe1,rw if reg.53h. bit 7=1 :tos[7:2]=16h 3:2 tos15 phe1,rw if reg.53h. bit 7=1 :tos[7:2]=15h 1:0 tos14 phe1,rw if reg.53h. bit 7=1 :tos[7:2]=14h reg. c6h: bit name default description 7:6 tos1b phe1,rw if reg.53h. bit 7=1 :tos[7:2]=1bh 5:4 tos1a phe1,rw if reg.53h. bit 7=1 :tos[7:2]=1ah 3:2 tos19 phe1,rw if reg.53h. bit 7=1 :tos[7:2]=19h 1:0 tos18 phe1,rw if reg.53h. bit 7=1 :tos[7:2]=18h reg. c7h: bit name default description 7:6 tos1f phe1,rw if reg.53h. bit 7=1 :tos[7:2]=1fh 5:4 tos1e phe1,rw if reg.53h. bit 7=1 :tos[7:2]=1eh 3:2 tos1d phe1,rw if reg.53h. bit 7=1 :tos[7:2]=1dh 1:0 tos1c phe1,rw if reg.53h. bit 7=1 :tos[7:2]=1ch reg. c8h: bit name default description 7:6 tos23 phe2,rw if reg.53h. bit 7=1 :tos[7:2]=23h 5:4 tos22 phe2,rw if reg.53h. bit 7=1 :tos[7:2]=22h 3:2 tos21 phe2,rw if reg.53h. bit 7=1 :tos[7:2]=21h 1:0 tos20 phe2,rw if reg.53h. bit 7=1 :tos[7:2]=20h reg. c9h: bit name default description 7:6 tos27 phe2,rw if reg.53h. bit 7=1 :tos[7:2]=27h 5:4 tos26 phe2,rw if reg.53h. bit 7=1 :tos[7:2]=26h 3:2 tos25 phe2,rw if reg.53h. bit 7=1 :tos[7:2]=25h 1:0 tos24 phe2,rw if reg.53h. bit 7=1 :tos[7:2]=24h
DM9006 2-port switch with processor interface 36 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 reg. cah: bit name default description 7:6 tos2b phe2,rw if reg.53h. bit 7=1 :tos[7:2]=2bh 5:4 tos2a phe2,rw if reg.53h. bit 7=1 :tos[7:2]=2ah 3:2 tos29 phe2,rw if reg.53h. bit 7=1 :tos[7:2]=29h 1:0 tos28 phe2,rw if reg.53h. bit 7=1 :tos[7:2]=28h reg. cbh: bit name default description 7:6 tos2f phe2,rw if reg.53h. bit 7=1 :tos[7:2]=2fh 5:4 tos2e phe2,rw if reg.53h. bit 7=1 :tos[7:2]=2eh 3:2 tos2d phe2,rw if reg.53h. bit 7 =1 :tos[7:2]=2dh 1:0 tos2c phe2,rw if reg.53h. bit 7 =1 :tos[7:2]=2ch reg. cch: bit name default description 7:6 tos33 phe3,rw if reg.53h. bit 7=1 :tos[7:2]=33h 5:4 tos32 phe3,rw if reg.53h. bit 7=1 :tos[7:2]=32h 3:2 tos31 phe3,rw if reg.53h. bit 7=1 :tos[7:2]=31h 1:0 tos30 phe3,rw if reg.53h. bit 7=1 :tos[7:2]=30h reg. cdh: bit name default description 7:6 tos37 phe3,rw if reg.53h. bit 7=1 :tos[7:2]=37h 5:4 tos36 phe3,rw if reg.53h. bit 7=1 :tos[7:2]=36h 3:2 tos35 phe3,rw if reg.53h. bit 7=1 :tos[7:2]=35h 1:0 tos34 phe3,rw if reg.53h. bit 7=1 :tos[7:2]=34h reg. ceh: bit name default description 7:6 tos3b phe3,rw if reg.53h. bit 7=1 :tos[7:2]=3bh 5:4 tos3a phe3,rw if reg.53h. bit 7=1 :tos[7:2]=3ah 3:2 tos39 phe3,rw if reg.53h. bit 7=1 :tos[7:2]=39h 1:0 tos38 phe3,rw if reg.53h. bit 7=1 :tos[7:2]=38h reg. cfh: bit name default description 7:6 tos3f phe3,rw if reg.53h. bit 7=1 :tos[7:2]=3fh 5:4 tos3e phe3,rw if reg.53h. bit 7=1 :tos[7:2]=3eh 3:2 tos3d phe3,rw if reg.53h. bit 7=1 :tos[7:2]=3dh 1:0 tos3c phe3,rw if reg.53h. bit 7 =1 :tos[7:2]=3ch
DM9006 2-port switch with processor interface preliminary datasheet 37 DM9006-13-ds-p01 september 1, 2009 6.55 vlan priority map registers (d0h~d1h) define the 3-bit of priority field valn mapping to 2-bit priority queue number. reg. d0h: bit name default description 7:6 tag3 phe1,rw vlan priority tag value = 03h 5:4 tag2 phe1,rw vlan priority tag value = 02h 3:2 tag1 phe0,rw vlan priority tag value = 01h 1:0 tag0 phe0,rw vlan priority tag value = 00h reg. d1h: bit name default description 7:6 tag7 phe3,rw vlan priority tag value = 07h 5:4 tag6 phe3,rw vlan priority tag value = 06h 3:2 tag5 phe2,rw vlan priority tag value = 05h 1:0 tag4 phe2,rw vlan priority tag value = 04h 6.56 memory data pre-fetch read command without address increment register (f0h) bit name default description 7:0 mrcmdx x,ro read data from rx sram. after the read of this command, the read pointer of internal sram is unchanged. and the DM9006 starts to pre-fetch the sram data to internal data buffers. 6.57 memory data read command with address increment register (f2h) when register ffh bit 7 is ?0?, register f5h value will be returned to 0000h, if 16k-byte boundary is reached. when register ffh bit 7 is ?1?, register f5h value will be returned to 0000h, if processor port receive memory byte boundary address rx memory size, defined in register 3fh with default 1f00h, is reached. bit name default description 7:0 mrcmd x,ro read data from rx sram. after the read of this command, the read pointer is increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit respectively) 6.58 memory data read address register (f4h) when register ffh bit 7 is ?0?, register f5h and f4h can be us ed as memory byte address to read internal 64k-byte memory. when register ffh bit 7 is ?1?, register f5h and f4h can be used as processor port receive memory byte address with memory space range from 0 to (rx memory size - 1), defined in register 3fh with default 1effh. bit name default description 7:0 mdral phs0,rw memory data read address low byte[7:0] 6.59 memory data read address register (f5h) bit name default description 7:0 mdrah50 phs0,rw memory data read byte address high byte[15:8] 6.60 memory data write command without address increment register (f6h) bit name default description 7:0 mwcmdx x,wo write data to tx sram. after the write of this command, the write pointer is unchanged
DM9006 2-port switch with processor interface 38 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 6.61 memory data write command with address increment register (f8h) when register ffh bit 7 is ?0?, register fbh value will be returned to 0000h, if 16k-byte boundary is reached. bit name default description 7:0 mwcmd x,wo write data to tx sram after the write of this command, the write pointer is increased by 1, 2, or 4, depends on the operator mode. (8-bit, 16-bit,32-bit respectively) 6.62 memory data write address register (fah) when register ffh bit 7 is ?0?, register fbh and fah can be used as memory byte address to write internal 64k-byte memory. when register ffh bit 7 is ?1?, register fbh and fah are reserved. the processor port transmit memory address is generated by DM9006 automatically. bit name default description 7:0 mdwal phs0,rw memory data write_ address low byte[7:0] 6.63 memory data write address register (fbh) bit name default description 7:0 mdwah phs0,rw memory data write byte address high byte[15:8] 6.64 tx packet length registers (fch~fdh) bit name default description 7:0 txplh phs0,rw tx packet length high byte 7:0 txpll phs0,rw tx packet length low byte 6.65 interrupt status register (feh) bit name default description 7 iomode t0, ro width processor data bus 0: 16-bit mode 1: 8-bit mode 6 reserved phs0,ro reserved 5 lnkchg phs0,rw/c1 link status change of port 0 or 1 4 cnt_err phs0,rw/c1 memory management error 3 roo phs0,rw/c1 receive overflow counter overflow 2 ros phs0,rw/c1 receive overflow 1 pt phs0,rw/c1 packet transmitted 0 pr phs0,rw/c1 packet received 6.66 interrupt mask register (ffh) bit name default description 7 txrx_en phs0,rw enable the sram read/write pointer used as transmit /receive address. 6 reserved p0,ro reserved 5 lnkchgi phs0,rw enable link status change of port 0 or 1interrupt 4 cnt_err phs0,rw/c1 enable memory management error interrupt 3 rooi phs0,rw enable receive overflow counter overflow interrupt 2 roi phs0,rw enable receive overflow interrupt 1 pti phs0,rw enable packet transmitted interrupt 0 pri phs0,rw enable packet received interrupt
DM9006 2-port switch with processor interface preliminary datasheet 39 DM9006-13-ds-p01 september 1, 2009 7. eeprom format name word description mac address 0~2 6 byte ethernet address auto load control 3 bit[1:0] = 01: accept setting of word4 and word5 bit[3:2] = 01: accept setting of word6 [4:0] bit[5:4] = reserved bit[7:6] = 01: accept setting of word7 [3:0] bit[9:8] = 01: accept setting of word8 [4:0] bit[11:10] = 01: accept setting of word7[13:8] bit[13:12] = reserved bit[15:14] = 01: accept setting of word7 [15:14] vendor id 4 2 byte vendor id (default: 0a46h) product id 5 2 byte product id (default: 9013h) pin control 6 when word 3 bit [3:2] =01, these bits can control the cs#, ior#, iow# and irq pins polarity. bit[0] 0: cs# pin is active low (default) 1: cs# pin is active high bit[1] 0: ior# pin is active low (default) 1: ior# pin is active high bit[2] 0: iow# pin is active low (default) 1: iow# pin is active high bit[3] 0: irq pin is active high (default) 1: irq pin is active low bit[4] 0: irq pin is force output (default) 1: irq pin is open-collected bit [15:5] = reserved phy control 7 bit[0] 0: the wol pin is active high (default) 1: the wol pin is active low bit[1] 0: the wol pin is in level mode (default) 1: the wol pin is in pulse mode bit[2] 0: magic wakeup event is disable (default) 1: magic wakeup event is enabled bit[3] 0: link change wakeup event is disable (default) 1: link change wakeup event is enabled bit[7:4] = reserved bit[8] = led mode 0: led in normal mode (default, description see chapter 5.5) 1: led be changed to following mode lnk0_led/lnk1_led active low indicates traffic active fdx0_led/fdx1_led active low indicates 100mbps mode
DM9006 2-port switch with processor interface 40 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 spd0_led/spd1_led active low indicates 10mbps mode bit[13:9] = set to 00000 for reserved bit[14] = port 1 auto-mdix control 1: on, 0: off(default on) bit[15] = port 0 auto-mdix control 1: on, 0: off(default on) reserved 8~15 reserved control 16 bit[1:0] = 01: accept setting of word 17,18 bit[3:2] = 01: accept setting of word 19~26 bit[5:4] = 01: accept setting of word 27~30 bit[7:6] = 01: accept setting of word 31 bit[9:8] = 01: accept setting of word 32~39 bit[11:10] = 01: accept setting of word 40~47 bit[13:12] = 01: accept setting of word 49~52 bit[15:14] = reserved, set to 0000 in application switch control 1 17 when word 16 bit [1:0] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. 52h bit [7:0] this word bit [15:8] will be loaded to reg. 53h bit [7:0] reserved 18 this word must be cleared to 0000, if word 16 bit [1:0]=01 port 0 control 1 19 when word 16 bit [3:2] is ?01?, after power on reset: this word bit [7:0] will be loaded to port 0 reg. 61h bit [7:0] this word bit [15:8] will be loaded to port 0 reg. 66h bit [7:0] port 0 control 2 20 when word 16 bit [3:2] is ?01?, after power on reset: this word bit [7:0] will be loaded to port 0 reg. 67h bit [7:0] this word bit [15:8] will be loaded to port 0 reg. 6dh bit [7:0] port 1 control 1 21 when word 16 bit [3:2] is ?01?, after power on reset: this word bit [7:0] will be loaded to port 1 reg. 61h bit [7:0] this word bit [15:8] will be loaded to port 1 reg. 66h bit [7:0] port 1 control 2 22 when word 16 bit [3:2] is ?01?, after power on reset: this word bit [7:0] will be loaded to port 1 reg. 67h bit [7:0] this word bit [15:8] will be loaded to port 1 reg. 6dh bit [7:0] port 2 control 1 23 when word 16 bit [3:2] is ?01?, after power on reset: this word bit [7:0] will be loaded to port 2 reg. 61h bit [7:0] this word bit [15:8] will be loaded to port 2 reg. 66h bit [7:0] port 2 control 2 24 when word 16 bit [3:2] is ?01?, after power on reset: this word bit [7:0] will be loaded to port 2 reg. 67h bit [7:0] this word bit [15:8] will be loaded to port 2 reg. 6dh bit [7:0] up port control 1 25 when word 16 bit [3:2] is ?01?, after power on reset: this word bit [7:0] will be loaded to port 3 reg. 61h bit [7:0] this word bit [15:8] will be loaded to port 3 reg. 66h bit [7:0] up port control 2 26 when word 16 bit [3:2] is ?01?, after power on reset: this word bit [7:0] will be loaded to port 3 reg. 67h bit [7:0] this word bit [15:8] will be loaded to port 3 reg. 6dh bit [7:0] port 0 vlan tag 27 when word 16 bit [5:4] is ?01?, after power on reset: this word bit [7:0] will be loaded to port 0 reg. 6eh bit [7:0] this word bit [15:8] will be loaded to port 0 reg. 6fh bit [7:0] port 1 vlan tag 28 when word 16 bit [5:4[ is ?01?, after power on reset: this word bit [7:0] will be loaded to port 1 reg. 6eh bit [7:0] this word bit [15:8] will be loaded to port 1 reg. 6fh bit [7:0] port 2 vlan tag 29 when word 16 bit [5:4] is ?01?, after power on reset: this word bit [7:0] will be loaded to port 2 reg. 6eh bit [7:0] this word bit [15:8] will be loaded to port 2 reg. 6fh bit [7:0]
DM9006 2-port switch with processor interface preliminary datasheet 41 DM9006-13-ds-p01 september 1, 2009 up port vlan tag 30 when word 16 bit [5:4] is ?01?, after power on reset: this word bit [7:0] will be loaded to port 3 reg. 6eh bit [7:0] this word bit [15:8] will be loaded to port 3 reg. 6fh bit [7:0] vlan priority map 31 when word 16 bit [7:6] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. d0h bit [7:0] this word bit [15:8] will be loaded to reg. d1h bit [7:0] port vlan group 0,1 32 when word 16 bit [9:8] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. b0h bit [7:0] this word bit [15:8] will be loaded to reg. b1h bit [7:0] port vlan group 2,3 33 when word 16 bit [9:8] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. b2h bit [7:0] this word bit [15:8] will be loaded to reg. b3h bit [7:0] port vlan group 4,5 34 when word 16 bit [9:8] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. b4h bit [7:0] this word bit [15:8] will be loaded to reg. b5h bit [7:0] port vlan group 6,7 35 when word 16 bit [9:8] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. b6h bit [7:0] this word bit [15:8] will be loaded to reg. b7h bit [7:0] port vlan group 8,9 36 when word 16 bit [9:8] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. b8h bit [7:0] this word bit [15:8] will be loaded to reg. b9h bit [7:0] port vlan group 10,11 37 when word 16 bit [9:8] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. bah bit [7:0] this word bit [15:8] will be loaded to reg. bbh bit [7:0] port vlan group 12,13 38 when word 16 bit [9:8] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. bch bit [7:0] this word bit [15:8] will be loaded to reg. bdh bit [7:0] port vlan group 14,15 39 when word 16 bit 9:8 is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. beh bit [7:0] this word bit [15:8] will be loaded to reg. bfh bit [7:0] tos priority map 0 40 when word 16 bit [11:10] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. c0h bit [7:0] this word bit [15:8] will be loaded to reg. c1h bit [7:0] tos priority map 1 41 when word 16 bit [11:10] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. c2h bit [7:0] this word bit [15:8] will be loaded to reg. c3h bit [7:0] tos priority map 2 42 when word 16 bit [11:10] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. c4h bit [7:0] this word bit [15:8] will be loaded to reg. c5h bit [7:0] tos priority map 3 43 when word 16 bit [11:10] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. c6h bit [7:0] this word bit [15:8] will be loaded to reg. c7h bit [7:0] tos priority map 4 44 when word 16 bit [11:10] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. c8h bit 7~0 this word bit [15:8] will be loaded to reg. c9h bit 7~0 tos priority map 5 45 when word 16 bit [11:10] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. cah bit [7:0] this word bit [15:8] will be loaded to reg. cbh bit [7:0] tos priority map 6 46 when word 16 bit [11:10] is ?01?, after power on reset: this word bit [7:0] will be loaded to reg. cch bit [7:0]
DM9006 2-port switch with processor interface 42 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 this word bit [15:8] will be loaded to reg. cdh bit [7:0] tos priority map 7 47 when word 16 bit [11:10] is ?01?, after power on reset: this word bit [7:0]0 will be loaded to reg. ceh bit [7:0] this word bit [15:8] will be loaded to reg. cfh bit [7:0] reserved 48 reserved port security control 49 when word 16 bit [13:12] is ?01?, after power on reset: this word bit [3:0] will be loaded to port 0 register 6ch bit [2:0] this word bit [7:4] will be loaded to port 1 register 6ch bit [2:0] this word bit [11:8] will be loaded to port 2 register 6ch bit [2:0] snooping control 1 50 when word 16 bit [13:12] is ?01?, after power on reset: this word bit [7:0] will be loaded to register 78h this word bit [15:8] will be loaded to register 79h snooping control 2 51 when word 16 bit [13:12] is ?01?, after power on reset: this word bit [7:0] will be loaded to register 7ah this word bit [15:8] will be loaded to register 7bh snooping control 3 52 when word 16 bit [13:12] is ?01?, after power on reset: this word bit [1:0] will be loaded to register 7ch bit [1:0]
DM9006 2-port switch with processor interface preliminary datasheet 43 DM9006-13-ds-p01 september 1, 2009 8. phy registers mii register description ad d name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset loop back speed select auto-n enable power down isolate restart auto-n full duplex coll. test reserved 00h contr ol 0 0 1 1 0 0 0 1 0 000_0000 t4 cap. tx fdx cap. tx hdx cap. 10 fdx cap. 10 hdx cap. reserved pream. supr. auto-n compl. remote fault auto-n cap. link status jabber detect extd cap. 01h statu s 0 1 1 1 1 0000 1 0 0 1 0 0 1 02h phyid1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 oui_lsb vndr_mdl mdl_rev 03h phyid2 101110 001011 0000 04h auto-ne g. advertis e next page flp rcv ack remote fault reserved fc adv t4 adv tx fdx adv tx hdx adv 10 fdx adv 10 hdx adv advertised protocol selector field 05h link part. ability lp next page lp ack lp rf reserved lp fc lp t4 lp tx fdx lp tx hdx lp 10 fdx lp 10 hdx link partner protocol selector field 06h auto-ne g. expansi on reserved pardet fault lp next pg able next pg able new pg rcv lp auton cap. 10h specifi ed config. bp 4b5b bp scr bp align bp_ad pok reserv edr tx reserv ed rmii mode force 100lnk rsvd . col led rpdct r-en reset st. mch pream. supr. sleep mode remote loopout 11h specifi ed conf/sta t 100 fdx 100 hdx 10 fdx 10 hdx reserv ed revers ed revers ed phy addr [4:0] auto-n. monitor bit [3:0] 12h 10t conf/sta t rsvd lp enable hbe enable sque enable jab enable serial reserved polarity reverse 13h pwdo r reserved pd10d rv pd100l pdchip pdcrm pdaeq pddrv pdecli pdeclo pd10 14h specifie d config tstse 1 tstse 2 force _txsd force _fef prea mblex tx10m _pwr nway _pwr reserv ed mdix_ cntl autone g_dlpbk mdix_fix value mdix_d own monsel 1 monsel 0 reserv ed pd_val ue 16h rcver receiver error counter 17h dis_con nect reversed disconnect_counter 1dh pscr reversed prea mble x amplit ude tx_p wr reversed 1eh data indirect data 1fh addr indirect address key to default in the register description that follows, the default column takes the form: , / where: : 1 bit set to logic one 0 bit set to logic zero x no default value : ro = read only, rw = read/write : sc = self clearing, p = value permanently set
DM9006 2-port switch with processor interface 44 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 8.1 basic mode control register (bmcr) ? 00h bit bit name default description 15 reset 0, rw/sc reset 1=software reset 0=normal operation this bit sets the status and controls the phy registers to their default states. this bit, which is self-clearing, will keep returning a value of one until the reset process is completed 14 loopback 0, rw loopback loop-back control register 1 = loop-back enabled 0 = normal operation when in 100mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data appears at the mii receive outputs 13 speed selection 1, rw speed select 1 = 100mbps 0 = 10mbps link speed may be selected either by this bit or by auto-negotiation. when auto-negotiation is enabled and bit 12 is set, this bit will return auto-negotiation selected medium type 12 auto-negotiation enable 1, rw auto-negotiation enable 1 = auto-negotiation is enabled, bit 8 and 13 will be in auto-negotiation status 11 power down 0, rw power down while in the power-down state, the phy should respond to management transactions. during the transition to power-down state and while in the power-down state, the phy should not generate spurious signals on the mii 1=power down 0=normal operation 10 isolate 0,rw isolate force to 0 in application. 9 restart auto-negotiation 0,rw/sc restart auto-negotiation 1 = restart auto-negotiation. re-initiates the auto-negotiation process. when auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. this bit is self-clearing and it will keep returning to a value of 1 until auto-negotiation is initiated by the DM9006. the operation of the auto-negotiation process will not be affected by the management entity that clears this bit 0 = normal operation 8 duplex mode 1,rw duplex mode 1 = full duplex operation. duplex selection is allowed when auto-negotiation is disabled (bit 12 of this register is cleared). with auto-negotiation enabled, this bi t reflects the duplex capability selected by auto-negotiation 0 = normal operation
DM9006 2-port switch with processor interface preliminary datasheet 45 DM9006-13-ds-p01 september 1, 2009 7 collision test 0,rw collision test 1 = collision test enabled. when set, this bit will cause the col signal to be asserted in response to the assertion of tx_en in internal mii interface. 0 = normal operation 6-0 reserved 0,ro reserved read as 0, ignore on write 8.2 basic mode status register (bmsr) ? 01h bit bit name default description 15 100base-t4 0,ro/p 100base-t4 capable 1 = DM9006 is able to perform in 100base-t4 mode 0 = DM9006 is not able to perform in 100base-t4 mode 14 100base-tx full-duplex 1,ro/p 100base-tx full duplex capable 1 = DM9006 is able to perform 100base-tx in full duplex mode 0 = DM9006 is not able to perform 100base-tx in full duplex mode 13 100base-tx half-duplex 1,ro/p 100base-tx half duplex capable 1 = DM9006 is able to perform 100base-tx in half duplex mode 0 = DM9006 is not able to perform 100base-tx in half duplex mode 12 10base-t full-duplex 1,ro/p 10base-t full duplex capable 1 = DM9006 is able to perform 10base-t in full duplex mode 0 = DM9006 is not able to perform 10base-tx in full duplex mode 11 10base-t half-duplex 1,ro/p 10base-t half duplex capable 1 = DM9006 is able to perform 10base-t in half duplex mode 0 = DM9006 is not able to perform 10base-t in half duplex mode 10-7 reserved 0,ro reserved read as 0, ignore on write 6 mf preamble suppression 1,ro mii frame preamble suppression 1 = phy will accept management frames with preamble suppressed 0 = phy will not accept management frames with preamble suppressed 5 auto-negotiation complete 0,ro auto-negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 4 remote fault 0, ro remote fault 1 = remote fault condition detected (cleared on read or by a chip reset). fault criteria and detection method is DM9006 implementation specific. this bit will set after the rf bit in the anlpar (bit 13, register address 05) is set 0 = no remote fault condition detected 3 auto-negotiation ability 1,ro/p auto configuration ability 1 = DM9006 is able to perform auto-negotiation 0 = DM9006 is not able to perform auto-negotiation 2 link status 0,ro link status 1 = valid link is established (for either 10mbps or 100mbps operation) 0 = link is not established the link status bit is implemented with a latching function, so that
DM9006 2-port switch with processor interface 46 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 the occurrence of a link failure condition causes the link status bit to be cleared and remain cleared until it is read via the management interface 1 jabber detect 0, ro jabber detect 1 = jabber condition detected 0 = no jabber this bit is implemented with a latching function. jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a DM9006 reset. this bit works only in 10mbps mode 0 extended capability 1,ro/p extended capability 1 = extended register capable 0 = basic register capable only 8.3 phy id identifier register #1 (phyid1) ? 02h the phy identifier registers #1 and #2 work together in a single identifier of the DM9006. the identifier consists of a concatenation of the organizationally unique identifier (oui), a vendor's model number, and a model revision number. davicom semiconductor's ieee assigned oui is 00606e. bit bit name default description 15-0 oui_msb <0181h> oui most significant bits this register stores bit 3 to 18 of the oui (00606e) to bit 15 to 0 of this register respectively. the most significant two bits of the oui are ignored (the ieee standard refers to these as bit 1 and 2) 8.4 phy id identifier register #2 (phyid2) ? 03h bit bit name default description 15-10 oui_lsb <101110>, ro/p oui least significant bits bit 19 to 24 of the oui (00606e) are mapped to bit 15 to 10 of this register respectively 9-4 vndr_mdl <001011>, ro/p vendor model number five bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) 3-0 mdl_rev <0000>, ro/p model revision number five bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 4) 8.5 auto-negotiation advertisement register (anar) ? 04h this register contains the advertised abilities of this DM9006 device as they will be transmitted to its link partner during auto-negotiation. bit bit name default description 15 np 0,ro/p next page indication 1 = next page available 0 = no next page available the DM9006 has no next page, so this bit is permanently set to 0 14 ack 0,ro acknowledge 1 = link partner ability data reception acknowledged
DM9006 2-port switch with processor interface preliminary datasheet 47 DM9006-13-ds-p01 september 1, 2009 0 = not acknowledged the DM9006's auto-negotiation state machine will automatically control this bit in the outgoing flp bursts and set it at the appropriate time during the auto-negotiation process. software should not attempt to write to this bit. 13 rf 0, rw remote fault 1 = local device senses a fault condition 0 = no fault detected 12-11 reserved x, rw reserved write as 0, ignore on read 10 fcs 1, rw flow control support 1 = controller chip supports flow control ability 0 = controller chip doesn?t support flow control ability 9 t4 0, ro/p 100base-t4 support 1 = 100base-t4 is supported by the local device 0 = 100base-t4 is not supported the DM9006 does not support 100base-t4 so this bit is permanently set to 0 8 tx_fdx 1, rw 100base-tx full duplex support 1 = 100base-tx full duplex is supported by the local device 0 = 100base-tx full duplex is not supported 7 tx_hdx 1, rw 100base-tx support 1 = 100base-tx half duplex is supported by the local device 0 = 100base-tx half duplex is not supported 6 10_fdx 1, rw 10base-t full duplex support 1 = 10base-t full duplex is supported by the local device 0 = 10base-t full duplex is not supported 5 10_hdx 1, rw 10base-t support 1 = 10base-t half duplex is supported by the local device 0 = 10base-t half duplex is not supported 4-0 selector <00001>, rw protocol selection bits these bits contain the binary encoded protocol selector supported by this node <00001> indicates that this device supports ieee 802.3 csma/cd 8.6 auto-negotiation link partner ability register (anlpar) ? 05h this register contains the advertised abilities of th e link partner when received during auto-negotiation. bit bit name default description 15 np 0, ro next page indication 1 = link partner, next page available 0 = link partner, no next page available 14 ack 0, ro acknowledge 1 = link partner ability data reception acknowledged 0 = not acknowledged the DM9006's auto-negotiation state machine will automatically control this bit from the incoming flp bursts. software should not attempt to write to this bit 13 rf 0, ro remote fault
DM9006 2-port switch with processor interface 48 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 1 = remote fault indicated by link partner 0 = no remote fault indicated by link partner 12-11 reserved 0, ro reserved read as 0, ignore on write 10 fcs 0, ro flow control support 1 = controller chip supports flow control ability by link partner 0 = controller chip doesn?t support flow control ability by link partner 9 t4 0, ro 100base-t4 support 1 = 100base-t4 is supported by the link partner 0 = 100base-t4 is not supported by the link partner 8 tx_fdx 0, ro 100base-tx full duplex support 1 = 100base-tx full duplex is supported by the link partner 0 = 100base-tx full duplex is not supported by the link partner 7 tx_hdx 0, ro 100base-tx support 1 = 100base-tx half duplex is supported by the link partner 0 = 100base-tx half duplex is no t supported by the link partner 6 10_fdx 0, ro 10base-t full duplex support 1 = 10base-t full duplex is supported by the link partner 0 = 10base-t full duplex is not supported by the link partner 5 10_hdx 0, ro 10base-t support 1 = 10base-t half duplex is supported by the link partner 0 = 10base-t half duplex is not supported by the link partner 4-0 selector <00000>, ro protocol selection bits link partner?s binary encoded protocol selector 8.7 auto-negotiation expansion register (aner) - 06h bit bit name default description 15-5 reserved 0, ro reserved read as 0, ignore on write 4 pdf 0, ro/lh local device parallel detection fault pdf = 1: a fault detected via parallel detection function. pdf = 0: no fault detected via parallel detection function 3 lp_np_able 0, ro link partner next page able lp_np_able = 1: link partner, next page available lp_np_able = 0: link partner, no next page 2 np_able 0,ro/p local device next page able np_able = 1: DM9006, next page available np_able = 0: DM9006, no next page DM9006 does not support this function, so this bit is always 0 1 page_rx 0, ro new page received a new link code word page received. this bit will be automatically cleared when the register (register 6) is read by management 0 lp_an_able 0, ro link partner auto-negotiation able a ?1? in this bit indicates that the link partner supports auto-negotiation
DM9006 2-port switch with processor interface preliminary datasheet 49 DM9006-13-ds-p01 september 1, 2009 8.8 davicom specified configuration register (dscr) ? 10h bit bit name default description 15 bp_4b5b 0,rw bypass 4b5b encoding and 5b4b decoding 1 = 4b5b encoder and 5b4b decoder function bypassed 0 = normal 4b5b and 5b4b operation 14 bp_scr 0, rw bypass scrambler/descrambler function 1 = scrambler and descrambler function bypassed 0 = normal scrambler and descrambler operation 13 bp_align 0, rw bypass symbol alignment function 1 = receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. transmit functions (symbol encoder and scrambler) bypassed 0 = normal operation 12 bp_adpok 0, rw bypass adpok force signal detector (sd) active. this register is for debug only, not release to customer 1: forced sd is ok, 0: normal operation 11 reserved rw reserved force to 0 in application 10 tx 1, rw 100base-tx mode control 1 = 100base-tx operation 0 = 100base-fx operation 9 reserved 0, ro reserved 8 reserved 0, rw reserved 7 f_link_100 0, rw force good link in 100mbps 1 = force 100mbps good link status 0 = normal 100mbps operation this bit is useful for diagnostic purposes 6 reserved 0, rw reserved force to 0 in application. 5 col_led 0, rw col led control (valid in phy test mode) 4 rpdctr-en 1, rw reduced power down control enable this bit is used to enable automatic reduced power down 1 = enable automatic reduced power down 0 = disable automatic reduced power down 3 smrst 0, rw reset state machine when writes 1 to this bit, all state machines of phy will be reset. this bit is self-clear after reset is completed 2 mfpsc 1, rw mf preamble suppression control mii frame preamble suppression control bit 1 = mf preamble suppression bit on 0 = mf preamble suppression bit off 1 sleep 0, rw sleep mode writing a 1 to this bit will cause phy entering the sleep mode and power down all circuit except osc illator and clock generator circuit. when waking up from sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset
DM9006 2-port switch with processor interface 50 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 0 rlout 0, rw remote loop out control when this bit is set to 1, the re ceived data will loop out to the transmit channel. this is useful for bit error rate testing 8.9 davicom specified configuration and status register (dscsr) ? 11h bit bit name default description 15 100fdx 1, ro 100m full duplex operation mode after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 mode is a 100m full duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 14 100hdx 1, ro 100m half duplex operation mode after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 mode is a 100m half duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 13 10fdx 1, ro 10m full duplex operation mode after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 mode is a 10m full duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 12 10hdx 1, ro 10m half duplex operation mode after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 mode is a 10m half duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 11 reserved 0, ro reserved read as 0, ignore on write 10 reserved 0,rw reserved 9 reserved 0,rw reserved 8-4 phyadr[4:0] 1, rw phy address bit 4:0 the first phy address bit transmitted or received is the msb of the address (bit 4). a station management entity connected to multiple phy entities must know the appropriate address of each phy auto-negotiation monitor bits these bits are for debug only. the auto-n egotiation status will be written to these bits. b3 b2 b1 b0 0 0 0 0 in idle state 0 0 0 1 ability match 0 0 1 0 acknowledge match 0 0 1 1 acknowledge match fail 0 1 0 0 consistency match 0 1 0 1 consistency match fail 0 1 1 0 parallel detects signal link ready 0 1 1 1 parallel detects signal link ready fail 3-0 anmb[3:0] 0, ro 1 0 0 0 auto-negotiation completed successfully
DM9006 2-port switch with processor interface preliminary datasheet 51 DM9006-13-ds-p01 september 1, 2009 8.10 10base-t configuration/status (10btcsr) ? 12h bit bit name default description 15 reserved 0, ro reserved read as 0, ignore on write 14 lp_en 1, rw link pulse enable 1 = transmission of link pulses enabled 0 = link pulses disabled, good link condition forced this bit is valid only in 10mbps operation 13 hbe 1,rw heartbeat enable 1 = heartbeat function enabled 0 = heartbeat function disabled when the DM9006 is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode) 12 squelch 1, rw squelch enable 1 = normal squelch 0 = low squelch 11 jaben 1, rw jabber enable enables or disables the jabber function when the DM9006 is in 10base-t full duplex or 10base-t transceiver loopback mode 1 = jabber function enabled 0 = jabber function disabled 10 serial 0, rw 10m serial mode (valid in phy test mode) force to 0, in application. 9-1 reserved 0, ro reserved read as 0, ignore on write 0 polr 0, ro polarity reversed when this bit is set to 1, it indicates that the 10mbps cable polarity is reversed. this bit is automatically set and cleared by 10base-t module 8.11 power down control register (pwdor) ? 13h bit bit name default description 15-9 reserved 0, ro reserved read as 0, ignore on write 8 pd10drv 0, rw vendor power down control test 7 pd100dl 0, rw vendor power down control test 6 pdchip 0, rw vendor power down control test 5 pdcrm 0, rw vendor power down control test 4 pdaeq 0, rw vendor power down control test 3 pddrv 0, rw vendor power down control test 2 pdedi 0, rw vendor power down control test 1 pdedo 0, rw vendor power down control test 0 pd10 0, rw vendor power down control test * when selected, the power down value is control by register 20.0
DM9006 2-port switch with processor interface 52 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 8.12 (specified config) register ? 14h bit bit name default description 15 tstse1 0,rw vendor test select 1 control 14 tstse2 0,rw vendor test select 2 control 13 force_txsd 0,rw force signal detect 1: force sd signal ok in 100m 0: normal sd signal. 12 force_fef 0,rw vendor test select control 11 preamblex 0,rw preamble saving control 0: when bit 10 is set, the 10base-t transmit preamble count is reduced. when bit 11 of register 1dh is set, 12-bit preamble is reduced; otherwise 22-bit preamble is reduced. 1: transmit preamble bit count is normal in 10base-t mode 10 tx10m_pwr 1,rw 10base-t mode transmit power saving control 1: enable transmit power saving in 10base-t mode 0: disable transmit power saving in 10base-t mode 9 nway_pwr 0,rw auto-negotiation power saving control 1: disable power saving during auto-negotiation period 0: enable power saving during auto-negotiation period 8 reserved 0, ro reserved read as 0, ignore on write 7 mdix_cntl mdi/mdix,ro the polarity of mdi/mdix value 1: mdix mode 0: mdi mode 6 autoneg_dpbk 0,rw auto-negotiation loopback 1: test internal digital auto-negotiation loopback 0: normal. 5 mdix_fix value 0, rw mdix_cntl force value: when mdix_down = 1, mdix_cntl value depend on the register value. 4 mdix_down 0,rw mdix down manual force mdi/mdix. 0: enable hp auto-mdix 1: disable hp auto-mdix , mdix_cntl value depend on reg.14h.bit5 3 monsel1 0,rw vendor monitor select 1 2 monsel0 0,rw vendor monitor select 0 1 reserved 0,rw reserved force to 0, in application. 0 pd_value 0,rw power down control value decision the value of each field reg.13h. 1: power down 0: normal
DM9006 2-port switch with processor interface preliminary datasheet 53 DM9006-13-ds-p01 september 1, 2009 8.13 davicom specified receive error counter register (recr) ? 16h bit bit name default description 15-0 rcv_ err_ cnt 0, ro receive error counter receive error counter that increments upon detection of rxer. clean by reading this register. 8.14 davicom specified disconnect counter register (discr) ? 17h bit bit name default description 15-8 reserved 0, ro reserved 7-0 disconnect counter 0, ro disconnect counter that increment upon detection of disconnection. clean by reading this register. 8.15 power saving control register (pscr) ? 1dh bit bit name default description 15-12 reserved 0,ro reserved 11 preamblex 0,rw preamble saving control when both bit 10 and 11 of register 14h are set, the 10base-t transmit preamble count is reduced. 1: 12-bit preamble is reduced. 0: 22-bit preamble is reduced. 10 amplitude 0,rw transmit amplitude control disabled 1: when cable is unconnected with link partner, the tx amplitude is reduced for power saving. 0: disable transmit amplitude reduce function 9 tx_pwr 0.rw transmit power saving control disabled 1: when cable is unconnected with link partner, the driving current of transmit is reduced for power saving. 0: disable transmit driving power saving function 8-0 reserved 0,ro reserved 8.16 davicom indirect data register (data) ? 1eh bit bit name default description 15-0 data 0, rw in-direct data register when write, data to register that addressing by addr when read, data from register that addressing by addr 8.17 davicom indirect addr register (addr) ? 1fh bit bit name default description 15-8 reserved 0, ro reserved 3-0 addr 0, rw in-direct addr register 1: addressing to power saving control register (same as reg 1dh) 2: reserved 3: reserved 4: addressing to tx amplitude control register
DM9006 2-port switch with processor interface 54 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 8.18 davicom indirect tx amplitude control register (tx_out_cntl) ? indirect-04h bit bit name default description 15-6 reserved 0, ro reserved 5-0 tx amplitude 0, rw tx amplitude control to tune the amplitude of tx +/-.
DM9006 2-port switch with processor interface preliminary datasheet 55 DM9006-13-ds-p01 september 1, 2009 9. functional description 9.1 processor bus and memory management function: 9.1.1 processor interface in the general processor mode, the chip selection is just coming from pin cs#. there are only two addressing ports through the access of the host interface. one port is the index port and the other is the data port. the index port is decoded by the cmd pin=0 and the data by the cmd pin=1. the contents of the index port are the register address of the data port. before the access of any register, the address of the register must be saved in the index port before. 9.1.2 direct memory access control the DM9006 provides dma capability to simplify the access of the internal memory. after the setting of the starting address of the internal memory and then issuing a dummy read/write command to load the current data to internal data buffer, the desired location of the internal memory can be accessed by the read/write command registers. the memory?s address will be increased wi th the size equal to the current operation mode (i.e. the byte or word mode) and the data of the next location will be loaded to internal data buffer automatically. it is noted that the data of the first access (the dummy read/write command) in a sequential burst should be ignored because that the data was the contents of the last read/write command. there are two configured types of internal memory which are controlled by bit 7 of imr. when the bit 7 of imr is set, the internal memory is used for transmit and receive buffers. the transmit buffer occupies 8k bytes. and the receive buffer occupies 7.75k bytes. both the transmit and receive buffer address need not to be programmed instead that they are managed by the DM9006 automatically. in transmit function, after power on reset or each time after the transmit command is issued (bit 0 of tcr is set), the next starting transmit buffer address is loaded. in receive function, the 7.75k-byte receive buffer can be treated as a continued logic memory space. the memory address will wrap to address 0 if the end of address is reached. when the bit 7 of imr is cleared, there is a 64k- byte memory space in the DM9006 can be accessed. this configured type of in ternal memory is used for testing only. the memory write address (register fah/fbh) and the memory read address (register f4h/f5h) represent the physical memory address of the DM9006 internal memory. it is noted that after the memory had been written by memory write command, the switch reset command (bit 6 of register 52h) should be set before normal switch function operation, since the controlled data in internal memory may be corrupted. 9.1.3 packet transmission there are two packets, sequentially named as index i and index ii, can be stored in the tx sram at the same time. the index register 02h controls the insertion of crc. the start address of transmission is 00h and the current packet is index i after software or hardware reset. firstly write data to the tx sram using the dma port and then write the byte count to byte count register at index register 0fch and 0fdh. set the bit 1 of control register. the DM9006 starts to transmit the index i packet. before the transmission of the index i packet ends, the data of the next (index ii) packet can be moved to tx sram. after the index i packet ends the transmission, write the byte count data of the index ii to byte_count register and then set the bit 1 of control register to transmit the index ii packet. the following packets, named index i, ii, i, ii? use the same way to be transmitted. 9.1.4 packet reception the rx sram is a ring data structure. each packet has a 4-byte header followed with the data of the reception packet which crc field is included. the format of the 4-byte header is 01h, status, byte_count low, and byte_count high. it is noted that the start address of each packet is in the proper address boundary which depends on the operation mode (byte or word mode).
DM9006 2-port switch with processor interface 56 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 9.2 switch function: 9.2.1 address learning the dm9016 stores mac addresses, port number and time stamp information in the hash-based address table. the table can learn up to 1k unicast address entries. the dm9016 provides two methods to learn address in the table, self-learning and manual learning. self-learning the self-learning mechanism means the dm9016 learn the mac addresses of incoming packets in real time without cpu?s assistance. the switch engine creates a new entry if incoming packet?s source address (sa) does not exist and the packet is valid (error-free). if sa was found and incoming port mismatch with port number in table, update the entry with sa and incoming port number. those entries will be created, updated or aged dynamically. besides, the dm9016 has an option to disable address learning for individual port. this feature can be set by bit 0 of register 65h. manual learning the dm9016 also provides manual learning mechanism with cpu?s assistance. the cpu can create, update or delete entry for flexible management. in addition to above, the entry can be set as static one that will not be aged-out forever. 9.2.2 address aging the time stamp information of address table is used in the aging process. the switch engine updates time stamp whenever the corresponding sa receives. the switch engine would delete the entry if its time stamp is not updated for a period of time. the period can be programmed or disabled through bit 0 & 1 of register 52h. 9.2.3 packet forwarding the DM9006 forwards the incoming packet according to following decision: (1). if da is multicast/broadcast, the packet is forwarded to all ports, except to the port on which the packet was received. (2). switch engine would look up address table based on da when incoming packets is unicast. if the da was not found in address table, the packet is treated as a multicast packet and forward to other ports. if the da was found and its destination port number is different to source port number, the packet is forward to destination port. (3). switch engine also look up vlan, port monitor setting and other forwarding constraints for the forwarding decision, more detail will discuss in later sections. the DM9006 will filter incoming packets under following conditions: (1). error packets, including crc errors, alignment errors, illegal size errors. (2). pause packets. (3). if incoming packet is unicast and its destination port number is equal to source port number. 9.2.4 inter-packet gap (ipg) ipg is the idle time between any two valid packets at the same port. the typical number is 96 bits time. in other word, the value is 9.6u sec for 10mbps and 960n sec for 100mbps. 9.2.5 back-off algorithm the DM9006 implements the binary exponential back-off algorithm in half-d uplex mode compliant to ieee standard 802.3. 9.2.6 late collision late collision is a type of collision. if a collision error occurs after the first 512 bit times of data are transmitted, the packet is dropped. 9.2.7 half duplex flow control the DM9006 supports ieee standard 802.3x flow control frames on both transmit and receive sides. on the receive side, the DM9006 will defer transmitting next normal frames, if it receives a pause frame from link partner. on the transmit side, the DM9006 issues pause frame with maximum pause time when internal resources such as received buffers, transmit queue and transmit descriptor ring are unavailable. once resources are available, the DM9006 sends out a pause frame with zero pause time allows traffic to resume immediately.
DM9006 2-port switch with processor interface preliminary datasheet 57 DM9006-13-ds-p01 september 1, 2009 9.2.8 full duplex flow control the DM9006 supports half-duplex backpressure. the inducement is the same as full duplex mode. when flow control is required, the DM9006 sends jam pattern, thus forcing a collision. the flow control ability can be set in bit 4 of register 61h. 9.2.9 partition mode the DM9006 provides a partition mode for each port, see bit 6 of register 61h. the port enters partition mode when more than 64 consecutive collisions are occurred. in partition mode the port continuous to transmit but it will not receive. the port returned to normal operation mode when a good packet is seen on the wire. the detail description of partition mode represent following: (1). entering partition state a port will enter the partition state when either of the following conditions occurs: z the port detects a collision on every one of 64 consecutive re-transmit attempts to the same packet. z the port detects a single collision which occurs for more than 512 bit times. z transmit defer timer time out, which indicates the transmitting packet is deferred to long. (2). while in partition state: the port will continue to transmit its pending packet, regardless of the collision detection, and will not allow the usual back-off algorithm. additional packets pending for transmission will be transmitted, while ignoring the internal collision indication. this frees up the ports transmit buffers which would otherwise be filled up at the expense of other ports buffers. the assumption is that the partition is signifying a system failure situation (bad connection/cable/station), thus dropping packets is a small price to pay vs. the cost of halting the switch due to a buffer full condition. (3). exiting from partition state the port exits from partition state, following the end of a successful packet transmission. a successful packet transmission is defined as no collisions were detected on the first 512 bits of the transmission. 9.2.10 broadcast storm filtering the DM9006 has an option to limit the traffic of broadcast or multicast packets, to protect the switch from lower bandwidth availability. there are two type of broadcast storm control, one is throttling broadcast packet only, the other includes multicast. this feature can be set through bit 1 of register 61h. the broadcast storm threshold can be programmed by eeprom or register 67h, the default setting is no broadcast storm protecting. 9.2.11 bandwidth control the DM9006 supports two type of bandwidth control for each port. one is the ingress and egress bandwidth rate can be control separately, the other is combined together, this function can be set through bit 3 of register 61h. the bandwidth control is disabled by default. for separated bandwidth control mode, the threshold rate is defined in register 66h. for combined mode, it is defined in register 67h. the behavior of bandwidth control as below: (1).for the ingress control, if flow control function is enabled, pause or jam packet will be transmitted. the ingress packets will be dropped if flow control is disabled. (2).for the egress control, the egress port will not transmit any packets. on the other hand, the ingress bandwidth of source port w ill be throttled that prevent packets from forwarding. (3).in combined mode, if the sum of ingress and egress bandwidth over threshold, the bandwidth will be throttled. 9.2.12 port monitoring support the DM9006 supports ?port monitoring? function on per port base, detail as below: (1). sniffer port and monitor port there is only one port can be selected as ?sniffer port? by register 52h, multiple ports can be set as ?receive monitor port? or ?transmit monitor port? in per-port register 65h. (2).receive monitor all packets received on the ?receive monitor port? are send a copy to ?sniffer port?. for example, port 0 is set as ?receive monitor port? and port 3 (processor port) is selected as ?sniffer port?. if a packet is received form port 0 and destined to port 1 after forwarding decision, the DM9006 will forward it to port 1 and processor port in the end. (3).transmit monitor all packets transmitted on the ?transmit monitor
DM9006 2-port switch with processor interface 58 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 port? are send a copy to ?sniffer port?. for example, port 1 is set as ?transmit monitor port? and processor port is selected as ?sniffer port?. if a packet is received from port 0 and predestined to port 1 after forwarding decision, the DM9006 will forward it to port 1 and processor port in the end. (4).exception the DM9006 has an optional setting that broadcast/multicast packets are not monitored (see bit 4 of register 65h). it?s useful to avoid unnecessary bandwidth.
DM9006 2-port switch with processor interface preliminary datasheet 59 DM9006-13-ds-p01 september 1, 2009 9.2.13 vlan support 9.2.13.1 port-based vlan the DM9006 supports port-based vlan as default, up to 16 groups. each port has a default vid called pvid (port vid, see register 6fh). the DM9006 used lsb 4-bytes of pvid as index and mapped to register b0h~bfh, to define the vlan groups. 9.2.13.2 802.1q-based vlan regarding ieee 802.1q standard, tag-based vlan uses an extra tag to identify the vlan membership of a frame across vlan-aware switch/router. a tagged frame is four bytes longer than an untagged frame and contains two bytes of tpid (tag protocol identifier) and two bytes of tci (tag control information). dest. src. length/type data dest. src. tpid data tci length / type priority cfi vid standard frame tagged frame 0x8100 2 bytes 3 bits 1 bits 12 bits the DM9006 also supports 16 802.1q-based vlan groups, as specified in bit 1 of register 53h. it?s obvious that the tagged packets can be assigned to several different vlans which are determined according to the vid inside the vlan tag. therefore, the operation is similar to port-based vlan. the DM9006 used lsb 4-bytes vid of received packet with vlan tag and vlan group mapping register (b0h~bfh) to configure the vlan partition. if the destination port of received packet is not same vlan group with received port, it will be discarded. 9.2.13.3 tag/untag user can define each port as tag port or un-tag port by bit 7 of register 6dh in 802.1q-based vlan mode. the operation of tag and un-tag can explain as below conditions: (1). receive untagged packet and forward to un-tag port. received packet will forward to destination port without modification. (2). receive tagged packet and forward to un-tag port. the DM9006 will remove the tag from the packet and recalculate crc before sending it out. (3). receive untagged packet and forward to tag port. the DM9006 will insert the pvid tag when an untagged packet enters the port, and recalculate crc before delivering it. (4). receive tagged packet and forward to tag port. received packet will forward to destination port without modification. 9.2.14 priority support the DM9006 supports quality of service (qos) mechanism for multimedia communication such as voip and video conferencing. the DM9006 provides three priority classifications: port-based, 802.1p-based and diffserv-based priority. see next section for more detail. the DM9006 offers four level queues for transmit on per-port based. the DM9006 provides two packet scheduling algorithms: weighted round-robin queuing and
DM9006 2-port switch with processor interface 60 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 strict priority queuing. weighted round-robin queuing (wrr) based on their priority and queue weight. queues with larger weights get more service than smaller. this mechanism can get highly efficient bandwidth and smooth the traffic. strict priority queuing (spq) based on priority only. the packet on the highest priority queue is transmitted first. the next highest-priority queue is work until last queue empties, and so on. this feature can be set in bit 5 of register 6dh. 9.2.14.1 port-based priority port based priority is the simplest scheme and as default. each port has a 2-bit priority value as index for splitting ingress packets to the corresponding transmit queue. this value can be set in bit 0 and 1 of register 6dh. 9.2.14.2 802.1p-based priority 802.1p priority can be disabled by bit 2 of register 6dh, it is enabled by default. the DM9006 extracts 3-bit priority field from received packet with 802.1p vlan tag, and maps this field against vlan priority map registers (d0h~d1h) to determine which transmit queue is designated. the vlan priority map is programmable. 9.2.14.3 diffserv-based priority diffserv based priority uses the most significant 6-bit of the tos field in standard ipv4 header, and maps this field against tos priority map registers (c0h~cfh) to determine which transmit queue is designated. the tos priority map is programmable too. in addition, user can only refer to most significant 3-bit of the tos field optionally, see bit 7 of register 53h. 9.2.15 address table accessing type of address table there are three types of address table in the dm9016. the description is represented below: (1). unicast address table this table is used for destination mac address lookup and source mac address learning. the table can have up to 1024 entries. if the table is full, the latest one will kick ou t the eldest one. the programming method can refer to next section. (2). multicast address table this table stores multicast addresses up to 256 entries and can be maintained by host cpu for custom filtering and forwarding multicast packets. if the table is full, the latest one will kick out the eldest one. all of entries in multicast address table are static one. in addition to host cpu, multicast address table can be manipulated by internal switch engine, if hardware-based igmp snooping function is enabled. (3). igmp membership table this table is used to establish ipv4 multicast forwarding rule under igmp protocol if hardware-based igmp snooping function is enabled. it is automatic maintained by internal engine according to snooping igmp control packets, and can only support to read out by the host cpu. the maximum of entries of table is 16. if the table is full, never join anymore. 9.2.16 access rules of address table the dm9016 the procedure and flow chart of entry write is described as following: entry write (1). check the busy bit of ethernet address control/status register 1 (reg70h.0) to seek the availability of access engine. waiting until engine is available and to keep on following. (2). write the mac address to the ethernet address data registers (reg71h~76h). (3). write the port number (if target is unicast address table) or port map (if target is multicast address table) to ethernet address data register (reg77h.[3:0]). (4). if need, write the entry?s attributes that includes both static and overriding to ethernet address control/status register 1 (reg77h). (5). write the ?write? command and assign the target table to ethernet address control/status register 1 (reg70h.[4:1]) to start the operation. (6). check the busy bit again, wait for available. (7). read the command status from ethernet address control/status register 1 (reg70h.[6:5]). entry delete (1). check the busy bit of ethernet address control/status register 1 (reg70h.0) to seek the availability of access engine. waiting until engine is available and to keep on following. (2). write the mac address to the ethernet address data register (reg71h~76h). (3). write the ?delete? command and assign the target table to ethernet address control/status register 1 (reg70h.[4:1]) to start the operation. (4). check the busy bit again, wait for available.
DM9006 2-port switch with processor interface preliminary datasheet 61 DM9006-13-ds-p01 september 1, 2009 busy reg70h.0 set mac address (reg71h~76h) set port number/mapping (reg77h) set static/dynamic* (reg77h) set overriding* (reg77h) entry write issue command (reg70h) busy reg70h.0 check status (reg70h.[6:5]) finish start 1 0 0 1 (5). read the command status from ethernet address control/status register 1 (reg70h.[6:5]). entry search (1). check the busy bit of ethernet address control/status register 1 (reg70h.0) to seek the availability of access engine. waiting until engine is available and to keep on following. (2). write the mac address to the ethernet address data register (reg71h~76h). (3). write the ?search? command and assign the target table to ethernet address control/status register 1 (reg70h.[4:1]) to start the operation. (4). check the busy bit again, wait for available. (5). read the command status from ethernet address control/status register 1 (reg70h.[6:5]). (6). read the port number or port map from ethernet address control/status register 2 (reg77h.[3:0]) (7). if need, read the entry sequence (the sequence number of entry in address table) from ethernet address data register (reg71h~72h). (8). if need, read the entry?s attributes that include static (unicast address table only), igmp signature (multicast address table only) and overriding from ethernet address control/status register 2 (77h.[6:4]). entry read (1). check the busy bit of ethernet address control/status register 1 (reg70h.0) to seek the availability of access engine. waiting until engine is available and to keep on following. (2). write the entry sequence to the ethernet address data register (reg71h~76h). (3). write the ?read? command and assign the target table to ethernet address control/status register 1 (reg70h.[4:1]) to start the operation. (4). check the busy bit again, wait for available. (5). read the command status from ethernet address control/status register 1 (70h.[6:5]). (6). read the port number or port map from ethernet address control/status register 2 (reg77h.[3:0]) (7). if target is unicast or multicast address table, read the entry?s mac address from ethernet address data register (reg71h~76h). if target is igmp membership table, read the entry sequence (the sequence number of entry in address table) from ethernet address data register (reg71h~72h). (8). if need, read the entry?s attributes that include static, igmp signature and overriding from ethernet address control/status register 2 (reg77h.[6:4]).
DM9006 2-port switch with processor interface 62 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 entry search busy reg70h.0 set mac address (reg71h~76h) issue command (reg70h) busy reg70h.0 check status (reg70h.[6:5]) read port number/mapping (reg77h) read entry sequence* (reg71-72h) read attribute* (reg77h) finish start 0 1 0 1 entry read busy reg70h.0 set entry sequence (reg71h~72h) issue command (reg70h) busy reg70h.0 check status (reg70h.[6:5]) read port number/mapping (reg77h) read mac address (reg71-76h) read entry sequence* (reg71-72h) read attribute* (reg77h) finish start 0 1 0 1
DM9006 2-port switch with processor interface preliminary datasheet 63 DM9006-13-ds-p01 september 1, 2009 9.2.17 igmp snooping igmp introduction the internet group management protocol (igmp) is a communications protocol used to manage the membership of internet protocol multicast groups. igmp is used by ip hosts and adjacent multicast routers to establish multicast group memberships. there are three versions of igmp, as defined by "request for comments" (rfc) documents of the internet engineering task force (ietf). igmp v1 is defined by rfc 1112, igmp v2 is defined by rfc 2236 and igmp v3 is defined by rfc 3376. igmp snooping is a feature that allows the switch to "listen in" on the igmp protocol conversation between hosts and routers. the igmp snooping switch hears an igmp report from a host with a given multicast group address. it adds the host's port number to the multicast list for that group, and when the switch hears an igmp leave, it removes the host's port from the table entry. finally, switch will only forward multicast traffic to the hosts interested in that traffic. therefore, this function can effectively reduce multicast traffic. hardware-based igmp snooping the dm9016 supports igmp v1/v2 snooping and the maximal group is 16 without any software effort. the dm9016 automatically manipulates and updates igmp membership table and multicast table according to igmp control packets, such as membership report and leave. if igmp membership table is full, the later incoming igmp membership report (join) packet will be ignored and the group address won?t be registered into multicast address table. after that, the unregistered ip multicast packets (the destination mac address can not be found in the multicast address table) will be treated as normal multicast packets by default. the additional forwarding control method can see the register reg78h.[6:5]. the dm9016 supports router ports auto-detect and auto-aging mechanism. the port which receives igmp query packets will be treated as router port by default. the router port also can be define as static one by user (see reg78h.4) and the port map of the router port can be programmed at reg79h.[2:0]. keep in mind that the up port (port 3) is never treated as router port. the dm9016 leaves the router port if the time (router present timeout, 400sec by default) is expired that the port never receives igmp query during this period. if receiving v1report or v2report (group join), dm9016 creates new or updates the entry. if receiving leave, dm9016 deletes the entry directly when fast leave is enabled, or waiting until timeout. dm9016 removes the entry that was never updated after the timer of host timeout (group membership interval) is expired. this timer is programmable in dm9016 and defined by rfc 2236 as ((the robustness variable) times (the query interval)) plus (one query response interval). the setting of the robustness variable and the query interval can see reg7ah and reg7bh. 9.2.18 port security dm9016 supports three types of port security function on each port, see the port security & stp register (reg6ch.[1:0]). (1). first lock: the dm9016 locks the source mac address of first received packet on the port and the disables the learning function in this mode. after that, on detecting incoming packet, the dm916 compares source mac address of incoming with the locked one. the dm9016 forwards the packet if match, or drops by default. if port?s link status is changed, the first received packet would be locked again after link on. it?s noticeable that the previous one was kept in address table until aging out or removed by user. (2). first link lock: the lock scheme is same as first lock except that don?t lock again when link status is changed. (3). assign lock: the dm9016 allows user to assign the locked entries by programming instead of dynamic learning. the port?s learning function is disabled in this mode. 9.2.19 ipv6 mld snooping the dm9016 forwards the ipv6 multicast listener discovery (mld) packets to the processor port when mld snooping is enabled and the mld packets meet following scenario:
DM9006 2-port switch with processor interface 64 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 power-on initialization blocking state listening state learning state forwarding state disabled state z ipv6 multicast packets. z the hop limit in ipv6 header is 1. z the next header in ipv6 header is 0x3a (icmpv6) or 0x00 (and next header of hop-by-hop option header is 0x3a). z the type in icmp header is 0x82 (multicast listener query), 0x83 (multicast listener report) or 0x84 (multicast listener done). 9.2.20 spanning tree protocol support the dm9016 supports spanning tree protocol and provides four types of port state, forwarding, disable, learning and blocking/listening, see the port security & stp register (reg6ch.[1:0]). this function needs the cooperation n with external cpu. the following figure is the port state diagram of spanning tree protocol. (1). disable state: z setting: reg6ch[5:4] = 2?b01 z description: the port will neither receive nor transmit any packets. learning is disabled. z software action: none. (2). blocking state: z setting: reg6ch[5:4] = 2?b11 z description: only the bpdus or overriding packet will be received and transmitted. leaning is disabled. z software action: in order to establish spanning tree, the receiving bpdus will be forward to processor port but the processor should not send bpdus to the port in this state. (3). listening state: z setting: reg6ch[5:4] = 2?b11 z description: only the bpdus and overriding packet will be received and transmitted. leaning is disabled. z software action: the receiving bpdus will be forward to processor port and the processor can send bpdus to the port in this state. (4). learning state: z setting: reg6ch[5:4] = 2?b10 z description: only the bpdus and overriding packet will be received and transmitted. leaning is enabled. z software action: the receiving bpdus will be forward to processor port and the processor can send bpdus to the port in this state. (5). forwarding state: z setting: reg6ch[5:4] = 2?b00 z description: the port participates in frame relay, learning, and sta calculation. z software action: the receiving bpdus will be forward to processor port and the processor can send bpdus to the port in this state.
DM9006 2-port switch with processor interface preliminary datasheet 65 DM9006-13-ds-p01 september 1, 2009 9.3 internal phy functions 9.3.1 100base-tx operation the transmitter section contains the following functional blocks: - 4b5b encoder - scrambler - parallel to serial converter - nrz to nrzi converter - nrzi to mlt-3 - mlt-3 driver 9.3.1.1 4b5b encoder the 4b5b encoder converts 4-bit (4b) nibble data generated by the mac reconciliation layer into a 5-bit (5b) code group for transmission, see reference table 1. this conversion is required for control and packet data to be combined in code groups. the 4b5b encoder substitutes the first 8 bits of the mac preamble with a j/k code-group pair (11000 10001) upon transmit. the 4b5b encoder continues to replace subsequent 4b preamble and data nibbles with corresponding 5b code-groups. at the end of the transmit packet, upon the deassertion of the transmit enable signal from the mac reconciliation layer, the 4b5b encoder injects the t/r code-group pair (01101 00111) indicating the end of frame. after the t/r code-group pair, the 4b5b encoder continuously injects idles into the transmit data stream until transmit enable is asserted and the next transmit packet is detected. 9.3.1.2 scrambler the scrambler is required to control the radiated emissions (emi) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100base-tx operation. by scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. without the scrambler, energy levels on the cable could peak beyond fcc limitations at frequencies related to the repeated 5b sequences, like the continuous transmission of idle symbols. the scrambler outp ut is combined with the nrz 5b data from the code-group encoder via an xor logic function. the result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. 9.3.1.3 parallel to serial converter the parallel to serial conv erter receives parallel 5b scrambled data from the scrambler, and serializes it (converts it from a parallel to a serial data stream). the serialized data stream is then presented to the nrz to nrzi encoder block 9.3.1.4 nrz to nrzi encoder after the transmit data stream has been scrambled and serialized, the data must be nrzi encoded for compatibility with the tp-p md standard, for 100base -tx transmission over category-5 unshielded twisted pair cable. 9.3.1.5 mlt-3 converter the mlt-3 conversion is accomplished by converting the data stream output, from the nrzi encoder into two binary data streams, with alternately phased logic one event. 9.3.1.6 mlt-3 driver the two binary data streams created at the mlt-3 converter are fed to the twisted pair output driver, which converts these streams to current sources and alternately drives either side of the transmit transformer?s primary winding , resulting in a minimal current mlt-3 signal.
DM9006 2-port switch with processor interface 66 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 9.3.1.7 4b5b code group symbol meaning 4b code 3210 5b code 43210 0 data 0 0000 11110 1 data 1 0001 01001 2 data 2 0010 10100 3 data 3 0011 10101 4 data 4 0100 01010 5 data 5 0101 01011 6 data 6 0110 01110 7 data 7 0111 01111 8 data 8 1000 10010 9 data 9 1001 10011 a data a 1010 10110 b data b 1011 10111 c data c 1100 11010 d data d 1101 11011 e data e 1110 11100 f data f 1111 11101 i idle undefined 11111 j sfd (1) 0101 11000 k sfd (2) 0101 10001 t esd (1) undefined 01101 r esd (2) undefined 00111 h error undefined 00100 v invalid undefined 00000 v invalid undefined 00001 v invalid undefined 00010 v invalid undefined 00011 v invalid undefined 00101 v invalid undefined 00110 v invalid undefined 01000 v invalid undefined 01100 v invalid undefined 10000 v invalid undefined 11001 table 1
DM9006 2-port switch with processor interface preliminary datasheet 67 DM9006-13-ds-p01 september 1, 2009 9.3.2 100base-tx receiver the 100base-tx receiver contains several function blocks that convert the scrambled 125mb/s serial data to synchronous 4-bit nibble data. the receive section contains the following functional blocks: - signal detect - digital adaptive equalization - mlt-3 to binary decoder - clock recovery module - nrzi to nrz decoder - serial to parallel - descrambler - code group alignment - 4b5b decoder 9.3.2.1 signal detect the signal detects function meets the specifications mandated by the ansi xt12 tp-pmd 100base-tx standards for both voltage thresholds and timing parameters. 9.3.2.2 adaptive equalization when transmitting data over copper twisted pair cable at high speed, attenuation based on frequency becomes a concern. in high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. this variation in signal attenuation, caused by frequency variations, must be compensated for to ensure the integrity of the received data. in order to ensure quality transmission when employing mlt-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. the selection of long cable lengths for a given implementation requires significant compensation, which will be over-killed in a situation that includes shorter, less attenuating cable lengths. conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. 9.3.2.3 mlt-3 to nrzi decoder the DM9006 decodes the mlt-3 information from the digital adaptive equalizer into nrzi data. 9.3.2.4 clock recovery module the clock recovery module accepts nrzi data from the mlt-3 to nrzi decoder. the clock recovery module locks onto the data stream and extracts the 125 mhz reference clock. the extracted and synchronized clock and data are presented to the nrzi to nrz decoder. 9.3.2.5 nrzi to nrz the transmit data stream is required to be nrzi encoded for compatibility wi th the tp-pmd standard for 100base-tx transmission over category-5 unshielded twisted pair cable. this conversion process must be reversed on the receive end. the nrzi to nrz decoder receives the nrzi data stream from the clock recovery module and converts it to a nrz data stream to be presented to the serial to parallel conversion block. 9.3.2.6 serial to parallel the serial to parallel converter receives a serial data stream from the nrzi to nrz converter. it converts the data stream to parallel da ta to be presented to the descrambler. 9.3.2.7 descrambler because of the scrambling process requires to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. the descrambler receives scrambled parallel data streams from the serial to parallel converter, and it descrambles the data streams, and presents the data streams to the code group alignment block.
DM9006 2-port switch with processor interface 68 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 9.3.2.8 code group alignment the code group alignment block receives un-aligned 5b data from the descrambler and converts it into 5b code group data. code group alignment occurs after the j/k is detected and subsequent data is aligned on a fixed boundary. 9.3.2.9 4b5b decoder the 4b5b decoder functions as a look-up table that translates incoming 5b code groups into 4b (nibble) data. when receiving a frame, the first 2 5-bit code groups receive the start-of-frame delimiter (j/k symbols). the j/k symbol pair is stripped and two nibbles of preamble pattern are substituted. the last two code groups are the end-of-frame delimiter (t/r symbols). the t/r symbol pair is also stripped from the nibble, presented to the reconciliation layer. 9.3.3 10base-t operation the 10base-t transceiver is ieee 802.3u compliant. when the DM9006 is operating in 10base-t mode, the coding scheme is manchester. data processed for transmit is presented in nibble format, converted to a serial bit stream, then the manchester encoded. when receiving, the bit stream, encoded by the manchester, is decoded and converted into nibble format. 9.3.4 collision detection for half-duplex operation, a collision is detected when the transmit and receive channels are active simultaneously. collision detection is disabled in full duplex operation. 9.3.5 carrier sense carrier sense (crs) is asserted in half-duplex operation during transmission or reception of data. during full-duplex mode, crs is asserted only during receive operations. 9.3.6 auto-negotiation the objective of auto-negotiation is to provide a means to exchange information between linked devices and to automatically configure both devices to take maximum advantage of their abilities. it is important to note that auto-negotiation does not test the characteristics of the linked segment. the auto-negotiation function provides a means for a device to advertise supported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. this allows devices on both ends of a segment to establish a link at the best common mode of operation. if more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function. auto-negotiation also provides a parallel detection function for devices that do not support the auto-negotiation feature. during parallel detection there is no exchange of information of configuration. instead, the receive signal is examined. if it is discovered that the signal matches a technology, which the receiving device supports, a connection will be automatically established using that technology. this allows devices not to support auto-negotiation but support a common mode of operation to establish a link.
DM9006 2-port switch with processor interface preliminary datasheet 69 DM9006-13-ds-p01 september 1, 2009 10. dc and ac electrical characteristics 10.1 absolute maximum ratings symbol parameter min. max. unit conditions vcc3 3.3v supply voltage -0.3 3.6 v - vcci 1.8v core power supply -0.3 1.95 v - avdd3 analog power supply 3.3v -0.3 3.6 v - avddi analog power supply 1.8v -0.3 1.95 v - v in dc input voltage (vin) -0.5 5.5 v - t stg storage temperature range -65 +150 c - t a ambient temperature 0 +70 c - l t lead temperature (tl, soldering, 10 sec.). - +260 c lead-free device 10.2 operating conditions symbol parameter min. typ. max. unit conditions vcc3 3.3v supply voltage 3.135 3.300 3.465 v - vcci 1.8v core power supply 1.71 1.80 1.89 v - avdd3 analog power supply 3.3v 3.135 3.300 3.465 v - avddi analog power supply 1.8v 1.71 1.80 1.89 v - - 230 - ma 1.8v only 100base-tx - 70 - ma 3.3v only - 140 - ma tx idle, 1.8v only - 250 - ma 50% utilization, 1.8v only - 360 - ma 100% utilization, 1.8v only 10base-tx - 30 - ma 3.3v only - 170 - ma 1.8v only p d (power dissipation) auto-negotiation or cable off - 40 - ma 3.3v only
DM9006 2-port switch with processor interface 70 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 10.3 dc electrical characteristics symbol parameter min. typ. max. unit conditions inputs vil input low voltage - - 0.8 v vcond1 vih input high voltage 2.0 - - v vcond1 iil input low leakage current -1 - - ua vin = 0.0v, vcond1 iih input high leakage current - - 1 ua vin = 3.3v, vcond1 outputs vol output low voltage - - 0.4 v iol =4ma voh output high voltage 2.4 - - v ioh = -4ma receiver vicm rx+/rx- common mode input voltage - 1.8 - v 100 termination across transmitter vtd100 100tx+/- differential output voltage 1.9 2.0 2.1 v peak to peak vtd10 10tx+/- differential output voltage 4.4 5 5.6 v peak to peak itd100 100tx+/- differential output current 19 20 21 ma absolute value itd10 10tx+/- differential output current 44 50 56 ma absolute value note: vcond1 = vcc3 = 3.3v, vcci = 1.8v, avdd3 = 3.3v, avddi = 1.8v.
DM9006 2-port switch with processor interface preliminary datasheet 71 DM9006-13-ds-p01 september 1, 2009 10.4 ac characteristics 10.4.1 power on reset timing pwrst# strap pins t2 t1 eecs t3 t4 t5 cs# symbol parameter min. typ. max. unit conditions t1 pwrst# low period 1 - - ms - t2 strap pin hold time with pwrst# 40 - - ns - t3 pwrst# high to eecs high - 5 - us - t4 pwrst# high to eecs burst end - -- 4 ms - t5 pwrst# high to cs# available -- 400 -- us -
DM9006 2-port switch with processor interface 72 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 10.4.2 processor i/o read timing ior# sd0~15 cs#,cmd t1 t2 t3 t4 t5 t6 symbol parameter min. typ. max. unit t1 cs#,cmd valid to ior# valid 5 ns t2 ior# invalid to cs#,cmd invalid 5 ns t3 ior# width 20 ns t4 ior# invalid to next ior#/iow# valid when read DM9006 register 2 clk *1 t4 ior# invalid to next ior#/iow# valid when read DM9006 memory with f0h register 4 clk *1 t3+t4 ior# invalid to next ior#/iow# valid when read DM9006 memory with f2h register 1 clk *1 t5 system data(sd) delay time 25 ns t6 ior# invalid to system data(sd) invalid 10 ns *1 : the unit: clk is under the internal system clock 50mhz.(20ns).
DM9006 2-port switch with processor interface preliminary datasheet 73 DM9006-13-ds-p01 september 1, 2009 10.4.3 processor i/o write timing iow# sd0~15 cs#,cmd t1 t2 t3 t4 t5 t6 symbol parameter min. typ. max. unit t1 cs#,cmd valid to iow# valid 5 ns t2 iow# invalid to cs#,cmd invalid 5 ns t3 iow# width 20 ns t4 iow# invalid to next iow#/ior# valid when write DM9006 index port 1 clk *1 t4 iow# invalid to next iow#/ior# valid when write DM9006 data port 2 clk *1 t3+t4 iow# invalid to next iow#/ior# valid when write DM9006 memory 1 clk *1 t5 system data(sd) setup time 5 ns t6 system data(sd) hold time 3 ns *1 : the unit: clk is under the internal system clock 50mhz.(20ns).
DM9006 2-port switch with processor interface 74 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 10.4.4 eeprom timing eecs eeck eedio t1 t2 t3 t4 t5 t6 t7 symbol parameter min. typ. max. unit t1 eecs setup time 480 ns t2 eecs hold time 2080 ns t3 eeck frequency 0.38 mhz t4 eedio setup time in output state 460 ns t5 eedio hold time in output state 2100 ns t6 eedio setup time in input state 8 ns t7 eedio hold time in input state 8 ns
DM9006 2-port switch with processor interface preliminary datasheet 75 DM9006-13-ds-p01 september 1, 2009 11. package information 64 pins lqfp package outline information: dimension in mm dimension in inch symbol min nom max min nom max a - - 1.60 - - 0.063 a 1 0.05 - 0.15 0.002 - 0.006 a 2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 b 1 0.17 0.20 0.23 0.007 0.008 0.009 c 0.09 - 0.20 0.004 - 0.008 c 1 0.09 - 0.16 0.004 - 0.006 d 12.00 bsc 0.472 bsc d 1 10.00 bsc 0.394 bsc e 12.00 bsc 0.472 bsc e 1 10.00 bsc 0.394 bsc e 0.50 bsc 0.020 bsc l 0.45 0.60 0.75 0.018 0.024 0.030 l 1 1.00 ref 0.039 ref r 1 0.08 - - 0.003 - - r 2 0.08 - 0.20 0.003 - 0.008 s 0.20 - - 0.008 - - 0 o 3.5 o 7 o 0 o 3.5 o 7 o 1 0 o - - 0 o - - 2 12 o typ 12 o typ 3 12 o typ 12 o typ 1. dimension d 1 and e 1 do not include resin fin. 2. all dimensions are base on metric system. 3. general appearance spec should base on its final visual inspection spec.
DM9006 2-port switch with processor interface 76 preliminary datasheet DM9006-13-ds-p01 september 1, 2009 12. ordering information part number pin count package DM9006ep 64 lqfp (pb-free) support lead-free and halogen?free disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by davicom semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. davicom makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. further, davicom makes no warranty of merchantability or fitness for any purpose. davicom reserves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. products described herein are intended for use in normal commercial applications. applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by davicom for such applications. please note that application circuits illustrate d in this document are for reference purposes only. davicom?s terms and conditions printed on the order acknowledgment govern all sales by davicom. davicom will not be bound by any terms inconsistent with these unless davicom agrees otherwise in writing. acceptance of the buyer?s orders shall be based on these terms. company overview davicom semiconductor inc. develops and manufactures integrated circuits for integration into data communication products. our mission is to design and produce ic products that are the industry?s best value for data, audio, video, and internet/intranet applications. to achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. products we offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and ethernet networking standards. contact windows for additional information about davicom products, contact the sales department at: headquarters hsin-chu office: no.6 li-hsin rd. vi, science-based park, hsin-chu city, taiwan, r.o.c. tel: + 886-3-5798797 fax: + 886-3-5646929 e-mail: sales@davicom.com.tw web: http://www.davicom.com.tw warning conditions beyond those listed for the absolute maximum may destroy or damage the products. in addition, conditions for sustai ned periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function .

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